Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and elim…

…inate condition copies"

This reverts commit r286171, it breaks piglit test fs-discard-exit-2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286530 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

@@ -440,7 +440,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
 
   setSchedulingPreference(Sched::RegPressure);
   setJumpIsExpensive(true);
-  setHasMultipleConditionRegisters(true);
 
   // SI at least has hardware support for floating point exceptions, but no way
   // of using or handling them is implemented. They are also optional in OpenCL

lib/Target/AMDGPU/SILowerI1Copies.cpp

@@ -121,31 +121,11 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
           }
         }
 
-        // If there are uses which are just a copy back from this new VReg_1
-        // to another SGPR_64 just forward propagate original SGPR_64.
-        SmallVector<MachineInstr *, 4> RegUses;
-        for (auto &Use : MRI.use_instructions(Dst.getReg()))
-          if (Use.isFullCopy())
-            RegUses.push_back(&Use);
-
-        while (!RegUses.empty()) {
-          MachineInstr *Use = RegUses.pop_back_val();
-          if (Use->getOperand(1).getReg() == Dst.getReg()) {
-            unsigned RegCopy = Use->getOperand(0).getReg();
-            if (!TargetRegisterInfo::isVirtualRegister(RegCopy))
-              continue;
-            Use->eraseFromParent();
-            MRI.replaceRegWith(RegCopy, Src.getReg());
-          }
-        }
-
-        if (!MRI.use_empty(Dst.getReg()))
-          BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
-            .addOperand(Dst)
-            .addImm(0)
-            .addImm(-1)
-            .addOperand(Src);
-
+        BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
+          .addOperand(Dst)
+          .addImm(0)
+          .addImm(-1)
+          .addOperand(Src);
         MI.eraseFromParent();
       } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
                  SrcRC == &AMDGPU::VReg_1RegClass) {

test/CodeGen/AMDGPU/branch-relaxation.ll

@@ -90,7 +90,7 @@ bb3:
 ; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch:
 ; GCN: s_load_dword [[CND:s[0-9]+]]
 ; GCN-DAG: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
-; GCN-DAG: v_cmp_eq_f32_e64 {{vcc|(s\[[0-9]+:[0-9]+\])}}, [[CND]], 0
+; GCN-DAG: v_cmp_eq_f32_e64 vcc, [[CND]], 0
 ; GCN: s_cbranch_vccz [[LONGBB:BB[0-9]+_[0-9]+]]
 
 ; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb0
@@ -492,8 +492,8 @@ ret:
 ; GCN: s_setpc_b64
 
 ; GCN: [[LONG_BR_DEST0]]
-; GCN: v_cmp_ne_u32_e32
-; GCN-NEXT: s_cbranch_vccz
+; GCN: s_cmp_eq_u32
+; GCN-NEXT: s_cbranch_scc0
 ; GCN: s_setpc_b64
 
 ; GCN: s_endpgm