New machine-mode timer facility

Mirroring Andrew's commit to reference-chip
bale-john · Jul 8, 2015 · e6a13cd · e6a13cd
1 parent 4fbb0f8
commit e6a13cd
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Showing 5 changed files with 4 additions and 4 deletions.
diff --git a/Makefrag b/Makefrag
@@ -162,7 +162,6 @@ asm_p_tests = \
 	rv64si-p-ma_addr \
 	rv64si-p-scall \
 	rv64si-p-sbreak \
-	rv64si-p-timer \
 	rv64ui-pm-lrsc \
 	rv64mi-p-csr \
 	rv64mi-p-mcsr \

diff --git a/riscv-tools b/riscv-tools
diff --git a/rocket b/rocket
diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala
@@ -98,6 +98,7 @@ class DefaultConfig extends ChiselConfig (
       case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
       case NCustomMRWCSRs => 0
       //Uncore Paramters
+      case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
       case LNEndpoints => site(TLNManagers) + site(TLNClients)
       case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
       case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)

diff --git a/uncore b/uncore