soc: x86: Add Raptor Lake SoC definition

Add a basic definition for the Raptor Lake SoC.

Signed-off-by: Yinfang Wang <[email protected]>

soc/x86/raptor_lake/CMakeLists.txt

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+zephyr_cc_option(-march=goldmont)

soc/x86/raptor_lake/Kconfig.defconfig

@@ -0,0 +1,21 @@
+# Raptor Lake SoC configuration options
+
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_RAPTOR_LAKE
+
+config SOC
+	default "raptor_lake"
+
+config PCIE_MMIO_CFG
+	default y
+
+config X86_DYNAMIC_IRQ_STUBS
+	default 16
+	depends on DYNAMIC_INTERRUPTS
+
+config UART_NS16550_ACCESS_IOPORT
+	default y if UART_NS16550
+
+endif # SOC_RAPTOR_LAKE

soc/x86/raptor_lake/Kconfig.soc

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+# Copyright (c) 2022 Intel Corporation Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RAPTOR_LAKE
+	bool "Intel Raptor Lake Soc"
+	select X86
+	select CPU_ATOM
+	select PCIE
+	select PCIE_MSI
+	select DYNAMIC_INTERRUPTS
+	select X86_MMU

soc/x86/raptor_lake/doc/supported_features.txt

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+Supported Features
+==================
+
+UART Serial Port Support
+-------------------------------------
+
+The Raptor Lake UARTs are NS16550-compatible. Baud rate of
+115.2kbps is supported on uart0.

soc/x86/raptor_lake/linker.ld

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+/*
+ * Copyright (c) 2022 Intel Corp.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/x86/memory.ld>
+
+#ifdef CONFIG_X86_64
+#include <zephyr/arch/x86/intel64/linker.ld>
+#else
+#include <zephyr/arch/x86/ia32/linker.ld>
+#endif /* CONFIG_X86_64 */

soc/x86/raptor_lake/soc.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the Raptor Lake SoC
+ *
+ * This header file is used to specify and describe soc-level aspects for
+ * the 'Raptor Lake' SoC.
+ */
+
+#ifndef __SOC_H_
+#define __SOC_H_
+
+#include <zephyr/sys/util.h>
+
+#ifndef _ASMLANGUAGE
+#include <zephyr/device.h>
+#include <zephyr/random/rand32.h>
+#endif
+
+#if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
+#include <zephyr/drivers/pcie/pcie.h>
+#define X86_SOC_EARLY_SERIAL_PCIDEV DT_REG_ADDR(DT_CHOSEN(zephyr_console))
+#else
+#define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
+#endif
+
+#endif /* __SOC_H_ */