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Improve log format. Re-order registers to allow for block read.
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@ultraembedded
ultraembedded committed Jan 30, 2016
1 parent 1a43d85 commit ca1d51b
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Showing 4 changed files with 76 additions and 78 deletions.
25 changes: 13 additions & 12 deletions usb_sniffer/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -13,14 +13,15 @@ Configuration of the IP is performed using a Wishbone slave interface.
* Dense logging format.
* Supports continuous streaming, one shot and detects buffer overruns.


##### Register Map

| Offset | Name | Description |
| ------ | ---- | ------------- |
| 0x00 | USB_BUFFER_CFG | [RW] Configuration Register |
| 0x04 | USB_BUFFER_STS | [R] Status Register |
| 0x08 | USB_BUFFER_BASE | [RW] Buffer Base Address |
| 0x0c | USB_BUFFER_END | [RW] Buffer End Address |
| 0x04 | USB_BUFFER_BASE | [RW] Buffer Base Address |
| 0x08 | USB_BUFFER_END | [RW] Buffer End Address |
| 0x0c | USB_BUFFER_STS | [R] Status Register |
| 0x10 | USB_BUFFER_CURRENT | [R] Buffer Current address |
| 0x14 | USB_BUFFER_READ | [RW] Buffer Read Address |

Expand All @@ -39,15 +40,6 @@ Configuration of the IP is performed using a Wishbone slave interface.
| 1 | CONT | Continuous capture - overwrite on wrap (0 = Stop on full, 1 = cont) |
| 0 | ENABLED | Capture enabled |

##### Register: USB_BUFFER_STS

| Bits | Name | Description |
| ---- | ---- | -------------- |
| 3 | OVERFLOW | Occurs when write pointer (BUFFER_CURRENT) hits read pointer (BUFFER_READ) |
| 2 | MEM_STALL | Overrun due to memory stall (data lost) |
| 1 | WRAPPED | Capture wrapped |
| 0 | TRIG | Capture triggered |

##### Register: USB_BUFFER_BASE

| Bits | Name | Description |
Expand All @@ -60,6 +52,15 @@ Configuration of the IP is performed using a Wishbone slave interface.
| ---- | ---- | -------------- |
| 31:0 | ADDR | Address of buffer end |

##### Register: USB_BUFFER_STS

| Bits | Name | Description |
| ---- | ---- | -------------- |
| 3 | OVERFLOW | Occurs when write pointer (BUFFER_CURRENT) hits read pointer (BUFFER_READ) |
| 2 | MEM_STALL | Overrun due to memory stall (data lost) |
| 1 | WRAPPED | Capture wrapped |
| 0 | TRIG | Capture triggered |

##### Register: USB_BUFFER_CURRENT

| Bits | Name | Description |
Expand Down
43 changes: 20 additions & 23 deletions usb_sniffer/rtl/usb_sniffer.v
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Original file line number Diff line number Diff line change
Expand Up @@ -44,11 +44,8 @@ module usb_sniffer
`define LOG_SOF_FRAME_W 11
`define LOG_SOF_FRAME_L 0
`define LOG_SOF_FRAME_H (`LOG_SOF_FRAME_L + `LOG_SOF_FRAME_W - 1)
`define LOG_SOF_CYCLE_W 16
`define LOG_SOF_CYCLE_L (`LOG_SOF_FRAME_H + 1)
`define LOG_SOF_CYCLE_H (`LOG_SOF_CYCLE_L + `LOG_SOF_CYCLE_W - 1)
`define LOG_RST_STATE_W 1
`define LOG_RST_STATE_L (`LOG_SOF_CYCLE_H + 1)
`define LOG_RST_STATE_L (`LOG_SOF_FRAME_H + 1)
`define LOG_RST_STATE_H (`LOG_RST_STATE_L + `LOG_RST_STATE_W - 1)

// TYPE = LOG_CTRL_TYPE_TOKEN | LOG_CTRL_TYPE_HSHAKE | LOG_CTRL_TYPE_DATA
Expand All @@ -66,7 +63,7 @@ module usb_sniffer
`define LOG_DATA_LEN_L (`LOG_TOKEN_PID_H + 1)
`define LOG_DATA_LEN_H (`LOG_DATA_LEN_L + `LOG_DATA_LEN_W - 1)

// TYPE = LOG_CTRL_TYPE_TOKEN | LOG_CTRL_TYPE_HSHAKE | LOG_CTRL_TYPE_DATA
// TYPE = LOG_CTRL_TYPE_TOKEN | LOG_CTRL_TYPE_HSHAKE | LOG_CTRL_TYPE_DATA | LOG_CTRL_TYPE_SOF
`define LOG_CTRL_CYCLE_W 8
`define LOG_CTRL_CYCLE_L 20
`define LOG_CTRL_CYCLE_H (`LOG_CTRL_CYCLE_L + `LOG_CTRL_CYCLE_W - 1)
Expand Down Expand Up @@ -540,20 +537,6 @@ else if (state_q == STATE_RX_TOKEN3 && sample_byte_w)
assign current_dev_w = token_data_q[6:0];
assign current_ep_w = token_data_q[10:7];

//-----------------------------------------------------------------
// Cycle Counter
//-----------------------------------------------------------------
reg [15:0] cycle_q;

always @ (posedge rst_i or posedge clk_i)
if (rst_i)
cycle_q <= 16'b0;
// Reset cycle counter every SOF
else if (state_q == STATE_RX_SOF_COMPLETE)
cycle_q <= 16'b0;
else if (cycle_q != 16'hFFFF)
cycle_q <= cycle_q + 16'd1;

//-----------------------------------------------------------------
// Data Counter
//-----------------------------------------------------------------
Expand All @@ -576,6 +559,8 @@ reg buffer_wr_q;
reg [31:0] buffer_r;
reg buffer_wr_r;

reg [15:0] cycle_q;

always @ *
begin
buffer_r = 32'b0;
Expand All @@ -584,9 +569,9 @@ begin
// Logging SOFs?
if (state_q == STATE_RX_SOF_COMPLETE && !cfg_ignore_sof_w)
begin
buffer_r[`LOG_SOF_FRAME_H:`LOG_SOF_FRAME_L] = frame_number_q;
buffer_r[`LOG_SOF_CYCLE_H:`LOG_SOF_CYCLE_L] = cycle_q;
buffer_r[`LOG_CTRL_TYPE_H:`LOG_CTRL_TYPE_L] = `LOG_CTRL_TYPE_SOF;
buffer_r[`LOG_SOF_FRAME_H:`LOG_SOF_FRAME_L] = frame_number_q;
buffer_r[`LOG_CTRL_CYCLE_H:`LOG_CTRL_CYCLE_L] = cycle_q[15:8];
buffer_r[`LOG_CTRL_TYPE_H:`LOG_CTRL_TYPE_L] = `LOG_CTRL_TYPE_SOF;
buffer_wr_r = 1'b1;
end
// Token
Expand All @@ -610,7 +595,7 @@ begin
else if (state_q == STATE_UPDATE_RST)
begin
buffer_r[`LOG_SOF_FRAME_H:`LOG_SOF_FRAME_L] = frame_number_q;
buffer_r[`LOG_SOF_CYCLE_H:`LOG_SOF_CYCLE_L] = cycle_q;
buffer_r[`LOG_CTRL_CYCLE_H:`LOG_CTRL_CYCLE_L] = cycle_q[15:8];
buffer_r[`LOG_RST_STATE_H:`LOG_RST_STATE_L] = usb_rst_q;
buffer_r[`LOG_CTRL_TYPE_H:`LOG_CTRL_TYPE_L] = `LOG_CTRL_TYPE_RST;
buffer_wr_r = 1'b1;
Expand Down Expand Up @@ -659,6 +644,18 @@ if (rst_i)
else if (!buffer_wr_q || !mem_stall_i)
buffer_wr_q <= buffer_wr_r;

//-----------------------------------------------------------------
// Cycle Counter: Delta ticks since last log entry
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i)
if (rst_i)
cycle_q <= 16'b0;
// Reset cycle counter on header write
else if (buffer_wr_r && (state_q != STATE_RX_DATA))
cycle_q <= 16'b0;
else if (cycle_q != 16'hFFFF)
cycle_q <= cycle_q + 16'd1;

//-----------------------------------------------------------------
// Enable Reset
//-----------------------------------------------------------------
Expand Down
52 changes: 26 additions & 26 deletions usb_sniffer/rtl/usb_sniffer_regs.v
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Original file line number Diff line number Diff line change
Expand Up @@ -20,12 +20,12 @@ module usb_sniffer_regs
output usb_buffer_cfg_ignore_sof_o,
output usb_buffer_cfg_cont_o,
output usb_buffer_cfg_enabled_o,
output [31:0] usb_buffer_base_addr_o,
output [31:0] usb_buffer_end_addr_o,
input usb_buffer_sts_overflow_i,
input usb_buffer_sts_mem_stall_i,
input usb_buffer_sts_wrapped_i,
input usb_buffer_sts_trig_i,
output [31:0] usb_buffer_base_addr_o,
output [31:0] usb_buffer_end_addr_o,
input [31:0] usb_buffer_current_addr_i,
output [31:0] usb_buffer_read_addr_o,

Expand Down Expand Up @@ -192,23 +192,6 @@ else if (write_en_w && (addr_i == `USB_BUFFER_CFG))
assign usb_buffer_cfg_enabled_o = usb_buffer_cfg_enabled_q;


//-----------------------------------------------------------------
// Register usb_buffer_sts
//-----------------------------------------------------------------
reg usb_buffer_sts_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_buffer_sts_wr_q <= 1'b0;
else if (write_en_w && (addr_i == `USB_BUFFER_STS))
usb_buffer_sts_wr_q <= 1'b1;
else
usb_buffer_sts_wr_q <= 1'b0;





//-----------------------------------------------------------------
// Register usb_buffer_base
//-----------------------------------------------------------------
Expand Down Expand Up @@ -259,6 +242,23 @@ else if (write_en_w && (addr_i == `USB_BUFFER_END))
assign usb_buffer_end_addr_o = usb_buffer_end_addr_q;


//-----------------------------------------------------------------
// Register usb_buffer_sts
//-----------------------------------------------------------------
reg usb_buffer_sts_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_buffer_sts_wr_q <= 1'b0;
else if (write_en_w && (addr_i == `USB_BUFFER_STS))
usb_buffer_sts_wr_q <= 1'b1;
else
usb_buffer_sts_wr_q <= 1'b0;





//-----------------------------------------------------------------
// Register usb_buffer_current
//-----------------------------------------------------------------
Expand Down Expand Up @@ -323,13 +323,6 @@ begin
data_r[`USB_BUFFER_CFG_CONT_R] = usb_buffer_cfg_cont_q;
data_r[`USB_BUFFER_CFG_ENABLED_R] = usb_buffer_cfg_enabled_q;
end
`USB_BUFFER_STS :
begin
data_r[`USB_BUFFER_STS_OVERFLOW_R] = usb_buffer_sts_overflow_i;
data_r[`USB_BUFFER_STS_MEM_STALL_R] = usb_buffer_sts_mem_stall_i;
data_r[`USB_BUFFER_STS_WRAPPED_R] = usb_buffer_sts_wrapped_i;
data_r[`USB_BUFFER_STS_TRIG_R] = usb_buffer_sts_trig_i;
end
`USB_BUFFER_BASE :
begin
data_r[`USB_BUFFER_BASE_ADDR_R] = usb_buffer_base_addr_q;
Expand All @@ -338,6 +331,13 @@ begin
begin
data_r[`USB_BUFFER_END_ADDR_R] = usb_buffer_end_addr_q;
end
`USB_BUFFER_STS :
begin
data_r[`USB_BUFFER_STS_OVERFLOW_R] = usb_buffer_sts_overflow_i;
data_r[`USB_BUFFER_STS_MEM_STALL_R] = usb_buffer_sts_mem_stall_i;
data_r[`USB_BUFFER_STS_WRAPPED_R] = usb_buffer_sts_wrapped_i;
data_r[`USB_BUFFER_STS_TRIG_R] = usb_buffer_sts_trig_i;
end
`USB_BUFFER_CURRENT :
begin
data_r[`USB_BUFFER_CURRENT_ADDR_R] = usb_buffer_current_addr_i;
Expand Down
34 changes: 17 additions & 17 deletions usb_sniffer/rtl/usb_sniffer_regs_defs.v
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,23 @@
`define USB_BUFFER_CFG_ENABLED_W 1
`define USB_BUFFER_CFG_ENABLED_R 0:0

`define USB_BUFFER_STS 8'h4
`define USB_BUFFER_BASE 8'h4

`define USB_BUFFER_BASE_ADDR_DEFAULT 0
`define USB_BUFFER_BASE_ADDR_B 0
`define USB_BUFFER_BASE_ADDR_T 31
`define USB_BUFFER_BASE_ADDR_W 32
`define USB_BUFFER_BASE_ADDR_R 31:0

`define USB_BUFFER_END 8'h8

`define USB_BUFFER_END_ADDR_DEFAULT 0
`define USB_BUFFER_END_ADDR_B 0
`define USB_BUFFER_END_ADDR_T 31
`define USB_BUFFER_END_ADDR_W 32
`define USB_BUFFER_END_ADDR_R 31:0

`define USB_BUFFER_STS 8'hc

`define USB_BUFFER_STS_OVERFLOW 3
`define USB_BUFFER_STS_OVERFLOW_DEFAULT 0
Expand Down Expand Up @@ -97,22 +113,6 @@
`define USB_BUFFER_STS_TRIG_W 1
`define USB_BUFFER_STS_TRIG_R 0:0

`define USB_BUFFER_BASE 8'h8

`define USB_BUFFER_BASE_ADDR_DEFAULT 0
`define USB_BUFFER_BASE_ADDR_B 0
`define USB_BUFFER_BASE_ADDR_T 31
`define USB_BUFFER_BASE_ADDR_W 32
`define USB_BUFFER_BASE_ADDR_R 31:0

`define USB_BUFFER_END 8'hc

`define USB_BUFFER_END_ADDR_DEFAULT 0
`define USB_BUFFER_END_ADDR_B 0
`define USB_BUFFER_END_ADDR_T 31
`define USB_BUFFER_END_ADDR_W 32
`define USB_BUFFER_END_ADDR_R 31:0

`define USB_BUFFER_CURRENT 8'h10

`define USB_BUFFER_CURRENT_ADDR_DEFAULT 0
Expand Down

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