tests: clock_control: stm32h7: pll2: Fix test configuration

In test spi1_pll2p_1, pll2 should be enabled instead of pll3. Signed-off-by: Erwan Gouriou <[email protected]>
benys · Jan 4, 2023 · 888607d · 888607d
1 parent a7743a4
commit 888607d
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/...ivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll2p_1.overlay b/...ivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll2p_1.overlay
@@ -9,7 +9,7 @@
  * It is assumed that it is applied after core_init.overlay file.
  */
 
-&pll3 {
+&pll2 {
 	clocks = <&clk_hse>;
 	div-m = <1>;
 	mul-n = <24>;