everywhere: fix typos

Fix a lot of typos

Signed-off-by: Nazar Kazakov <[email protected]>

.github/ISSUE_TEMPLATE/ext-source.md

@@ -18,7 +18,7 @@ Brief description of what this software does
 
 ## Mode of integration
 
-Describe whether you'd like to integrate this exernal component in the main tree
+Describe whether you'd like to integrate this external component in the main tree
 or as a module, and why. If the mode of integration is a module, suggest a
 repository name for the module
 

arch/arc/core/mpu/arc_mpu_v4_internal.h

@@ -132,7 +132,7 @@ static inline bool _is_user_accessible_region(uint32_t r_index, int write)
 	return false;
 }
 #else /* CONFIG_ARC_NORMAL_FIRMWARE */
-/* the following functions are prepared for SECURE_FRIMWARE */
+/* the following functions are prepared for SECURE_FIRMWARE */
 static inline void _region_init(uint32_t index, uint32_t region_addr, uint32_t size,
 				uint32_t region_attr)
 {

arch/arc/core/secureshield/arc_sjli.c

@@ -34,7 +34,7 @@ static void _default_sjli_entry(void)
 }
 
 /*
- * @brief initializaiton of sjli related functions
+ * @brief initialization of sjli related functions
  *
  */
 static void sjli_table_init(void)
@@ -46,7 +46,7 @@ static void sjli_table_init(void)
 }
 
 /*
- * @brief initializaiton of secureshield related functions.
+ * @brief initialization of secureshield related functions.
  */
 static int arc_secureshield_init(const struct device *arg)
 {

arch/arc/include/kernel_arch_data.h

@@ -159,7 +159,7 @@ struct _callee_saved_stack {
 
 #endif
 	/*
-	 * No need to save r31 (blink), it's either alread pushed as the pc or
+	 * No need to save r31 (blink), it's either already pushed as the pc or
 	 * blink on an irq stack frame.
 	 */
 };

arch/arm/core/aarch32/cortex_m/Kconfig

@@ -7,7 +7,7 @@
 # if CPU_CORTEX_M block so that SoCs can select which core they are using
 # without having to select all the options related to that core.  Everything
 # else is captured inside the if CPU_CORTEX_M block so they are not exposed
-# if one select a differnet ARM Cortex Family (Cortex-A or Cortex-R)
+# if one select a different ARM Cortex Family (Cortex-A or Cortex-R)
 
 config CPU_CORTEX_M0
 	bool
@@ -409,7 +409,7 @@ config NULL_POINTER_EXCEPTION_DETECTION_MPU
 	  CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)
 	  is not unmapped (covered by an MPU region already).
 	  If it is unmapped null-pointer dereferencing may
-	  still be idirectly detected (e.g. via a precise
+	  still be indirectly detected (e.g. via a precise
 	  Bus access fault), but this is not guaranteed. A
 	  build-time message warns the user of this scenario.
 

arch/arm/core/aarch32/cortex_m/timing.c

@@ -63,7 +63,7 @@ static inline uint64_t z_arm_dwt_freq_get(void)
 
 			/*
 			 * cycles are in 32-bit, and delta must be
-			 * calculated in 32-bit percision. Or it would
+			 * calculated in 32-bit precision. Or it would be
 			 * wrapping around in 64-bit.
 			 */
 			dcyc = (uint32_t)cyc_end - (uint32_t)cyc_start;

arch/arm/core/aarch32/fatal.c

@@ -74,7 +74,7 @@ void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
  * - We expect the supplied exception stack frame to always be a valid
  *   frame. That is because, if the ESF cannot be stacked during an SVC,
  *   a processor fault (e.g. stacking error) will be generated, and the
- *   fault handler will executed insted of the SVC.
+ *   fault handler will executed instead of the SVC.
  *
  * @param esf exception frame
  */

arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h

@@ -583,7 +583,7 @@ static int mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition
 #else
 
 	/* We are going to skip the full partition of the background areas.
-	 * So we can disable MPU regions inside which dynamic memroy regions
+	 * So we can disable MPU regions inside which dynamic memory regions
 	 * may be programmed.
 	 */
 	for (int i = 0; i < MPU_DYNAMIC_REGION_AREAS_NUM; i++) {

arch/posix/include/asm_inline_gcc.h

@@ -1 +1 @@
-/* EMTPTY ON PURPOSE. Why do the intel and ARM arch have 2 versions of it? */
+/* EMPTY ON PURPOSE. Why do the intel and ARM arch have 2 versions of it? */

arch/posix/include/posix_cheats.h

@@ -12,7 +12,7 @@
  *
  * Most users will be normally unaware of this file existence, unless they have
  * a link issue in which their POSIX functions calls are reported in errors (as
- * zap_<origian_func_name>).
+ * zap_<original_func_name>).
  * If you do see a link error telling you that zap_something is undefined, it is
  * likely that you forgot to select the corresponding Zephyr POSIX API.
  *

arch/x86/core/ia32/gdbstub.c

@@ -196,7 +196,7 @@ size_t arch_gdb_reg_writeone(struct gdb_ctx *ctx, uint8_t *hex, size_t hexlen,
 
 	if (regno == GDB_ORIG_EAX) {
 		/* GDB requires orig_eax that seems to be
-		 * Linux specific. Unfortunely if we just
+		 * Linux specific. Unfortunately if we just
 		 * return error, GDB will stop working.
 		 * So just fake an OK response by saying
 		 * that we have processed the hex string.

arch/x86/gen_gdt.py

@@ -75,7 +75,7 @@ def error(text):
 
 def create_gdt_pseudo_desc(addr, size):
     """Create pseudo GDT descriptor"""
-    debug("create pseudo decriptor: %x %x" % (addr, size))
+    debug("create pseudo descriptor: %x %x" % (addr, size))
     # ...and take back one byte for the Intel god whose Ark this is...
     size = size - 1
     return struct.pack(GDT_PD_FMT, size, addr, 0)

arch/x86/gen_mmu.py

@@ -608,7 +608,7 @@ def parse_args():
     parser.add_argument("--map", action='append',
                         help=textwrap.dedent('''\
                             Map extra memory:
-                            <physical address>,<size>[,<flags:LUWXD>[,<virtual adderss>]]
+                            <physical address>,<size>[,<flags:LUWXD>[,<virtual address>]]
                             where flags can be empty or combination of:
                                 L - Large page (2MB or 4MB),
                                 U - Userspace accessible,

arch/x86/include/ia32/exception.h

@@ -33,7 +33,7 @@
 /* Unfortunately, GCC extended asm doesn't work at toplevel so we need
  * to stringify stuff.
  *
- * What we are doing here is generating entires in the .intList section
+ * What we are doing here is generating entries in the .intList section
  * and also the assembly language stubs for the exception. We use
  * .gnu.linkonce section prefix so that the linker only includes the
  * first one of these it encounters for a particular vector. In this

arch/x86/timing.c

@@ -30,7 +30,7 @@ void arch_timing_x86_init(void)
 
 		/*
 		 * cycles are in 32-bit, and delta must be
-		 * calculated in 32-bit percision. Or it would
+		 * calculated in 32-bit precision. Or it would be
 		 * wrapping around in 64-bit.
 		 */
 		dcyc = (uint32_t)cyc_end - (uint32_t)cyc_start;

arch/x86/zefi/README.txt

@@ -46,7 +46,7 @@ Linux toolchain.  EFI binaries are relocatable PE-COFF files --
 basically Windows DLLs.  But our compiler only generates code for ELF
 targets.
 
-These environments differ in the way they implemenqt position
+These environments differ in the way they implement position
 independent code.  Non-static global variables and function addresses
 in ELF get found via GOT and PLT tables that are populated at load
 time by a system binary (ld-linux.so).  But there is no ld-linux.so in

arch/xtensa/include/xtensa-asm2-s.h

@@ -38,7 +38,7 @@
  *   context.
  *
  * - If the WOE bit is not enabled (for example, in code written for
- *   the CALL0 ABI), this becomes a silent noop and operates compatbily.
+ *   the CALL0 ABI), this becomes a silent noop and operates compatibly.
  *
  * - In memory protection situations, this relies on the existing
  *   exception handlers (and thus their use of the L/S32E

boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts

@@ -124,7 +124,7 @@ zephyr_udc0: &usbd {
 	compatible = "nordic,nrf-usbd";
 	status = "okay";
 };
-// All PWM's should be enaled
+// All PWM's should be enabled
 &pwm0 {
 	status = "okay";
 };

boards/arm/bl654_sensor_board/doc/bl654_sensor_board.rst

@@ -121,7 +121,7 @@ The sensor can be powered directly from a coin cell or from a voltage supplied
 on the UART pins, the board accepts voltage from 1.8v-3.3v. Note that if using a
 battery with a UART/debugger connected, the voltage of the UART/debugger (if it
 does not automatically sense/adjust) must be within 0.3v of the voltage of the
-coin cell to prevent supression diodes in the nRF52840 silicon being activated
+coin cell to prevent suppression diodes in the nRF52840 silicon being activated
 or possible back-powering of the battery.
 
 To power the board from an external source via UART, the solder bridge SB1 must

boards/arm/ip_k66f/linker.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 DENX Software Engineeering GmbH
+ * Copyright (c) 2021 DENX Software Engineering GmbH
  *
  * SPDX-License-Identifier: Apache-2.0
  */

boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts

@@ -161,7 +161,7 @@
 	/* LM75ADP temperature sensor on addr 0x48 */
 };
 
-/* Attention!: the spi-sck pin is in confict with the boot_button on pb13 */
+/* Attention!: the spi-sck pin is in conflict with the boot_button on pb13 */
 &spi2 {
 	pinctrl-0 = <&spi2_nss_pb9 &spi2_sck_pb13
 		     &spi2_miso_pb14 &spi2_mosi_pa10>;

boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts

@@ -65,7 +65,7 @@
 	flag = <NPCX_PSL_FALLING_EDGE>;
 };
 
-/* Overwirte default device properties with overlays in board dt file here. */
+/* Overwrite default device properties with overlays in board dt file here. */
 &uart1 {
 	status = "okay";
 	current-speed = <115200>;

boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts

@@ -77,7 +77,7 @@
 	flag = <NPCX_PSL_FALLING_EDGE>;
 };
 
-/* Overwirte default device properties with overlays in board dt file here. */
+/* Overwrite default device properties with overlays in board dt file here. */
 &uart1 {
 	status = "okay";
 	current-speed = <115200>;

boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig

@@ -12,8 +12,8 @@ config BOARD
 # To let the nRF5 bootloader load an application, the application
 # must be linked after Nordic MBR, that is factory-programmed on the board.
 
-# Nordic nRF5 booatloader exists outside of the partitions specified in the
-# DTS file, so we manually override FLASH_LOAD_OFFEST to link the application
+# Nordic nRF5 bootloader exists outside of the partitions specified in the
+# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application
 # correctly, after Nordic MBR.
 
 # When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION

boards/arm/nucleo_f746zg/nucleo_f746zg.dts

@@ -12,7 +12,7 @@
 /*
  * WARNING: The pin PA7 will conflict on selection of SPI_1 and ETH_STM32_HAL.
  *          If you require both peripherals, and you do not need Arduino Uno v3
- *          comaptability, the pin PB5 (also on ST Zio connector) can be used
+ *          compatibility, the pin PB5 (also on ST Zio connector) can be used
  *          for the SPI_1 MOSI signal.
  */
 

boards/arm/nucleo_f756zg/nucleo_f756zg.dts

@@ -12,7 +12,7 @@
 /*
  * WARNING: The pin PA7 will conflict on selection of SPI_1 and ETH_STM32_HAL.
  *          If you require both peripherals, and you do not need Arduino Uno v3
- *          comaptability, the pin PB5 (also on ST Zio connector) can be used
+ *          compatibility, the pin PB5 (also on ST Zio connector) can be used
  *          for the SPI_1 MOSI signal.
  */
 

boards/arm/nucleo_f767zi/nucleo_f767zi.dts

@@ -12,7 +12,7 @@
 /*
  * WARNING: The pin PA7 will conflict on selection of SPI_1 and ETH_STM32_HAL.
  *          If you require both peripherals, and you do not need Arduino Uno v3
- *          comaptability, the pin PB5 (also on ST Zio connector) can be used
+ *          compatibility, the pin PB5 (also on ST Zio connector) can be used
  *          for the SPI_1 MOSI signal.
  */
 

boards/arm/thingy53_nrf5340/board.c

@@ -103,7 +103,7 @@ static int setup(const struct device *dev)
 		 * sensors require, 2ms and 1ms power on delay respectively. In order not to sum
 		 * delays, common delay is introduced in the board start up file. This code is
 		 * executed after sensors are powered up and before their initialization.
-		 * It's ensured by build asserts at the beggining of this file.
+		 * It's ensured by build asserts at the beginning of this file.
 		 */
 		k_msleep(2);
 	}

boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig

@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-# The Zephyr build from this defconfig is execpted to boot from
+# The Zephyr build from this defconfig is expected to boot from
 # Intel Arm Trusted Firmware (ATF)
 # Boot Flow: BL21 -> BL31 -> Zephyr
 

boards/arm64/xenvm/xenvm.dts

@@ -7,7 +7,7 @@
  *
  * # LIBXL_DEBUG_DUMP_DTB=domu-libxl.dtb xl create zephyr.conf
  *
- * decompilling resulting domu-libxl.dtb and then manually aligning it
+ * decompiling resulting domu-libxl.dtb and then manually aligning it
  * with zephyr requirements.
  */
 

boards/posix/native_posix/board_soc.h

@@ -7,7 +7,7 @@
  * @file Extra definitions provided by the board to soc.h
  *
  * Background:
- * The POSIC ARCH/SOC/board layering is different than in normal archs
+ * The POSIX ARCH/SOC/board layering is different than in normal archs
  * The "SOC" does not provide almost any of the typical SOC functionality
  * but that is left for the "board" to define it
  * Device code may rely on the soc.h defining some things (like the interrupts

boards/posix/native_posix/timer_model.c

@@ -174,7 +174,7 @@ void hwtimer_cleanup(void)
 }
 
 /**
- * Enable the HW timer tick interrupts with a period <period> in micoseconds
+ * Enable the HW timer tick interrupts with a period <period> in microseconds
  */
 void hwtimer_enable(uint64_t period)
 {
@@ -373,7 +373,7 @@ void hwtimer_get_pseudohost_rtc_time(uint32_t *nsec, uint64_t *sec)
 	/*
 	 * Note: long double has a 64bits mantissa in x86.
 	 * Therefore to avoid loss of precision after 500 odd years into
-	 * the epoc, we first calculate the offset from the last adjustment
+	 * the epoch, we first calculate the offset from the last adjustment
 	 * time split in us and ns. So we keep the full precision for 500 odd
 	 * years after the last clock ratio adjustment (or native_posix boot,
 	 * whichever is latest).

boards/posix/native_posix/tracing.c

@@ -45,7 +45,7 @@ void posix_print_trace(const char *format, ...)
 }
 
 /**
- * Are stdout and stderr connectd to a tty
+ * Are stdout and stderr connected to a tty
  * 0  = no
  * 1  = yes
  * -1 = we do not know yet

boards/riscv/m2gl025_miv/m2gl025_miv_defconfig

@@ -12,5 +12,5 @@ CONFIG_RISCV_MACHINE_TIMER=y
 CONFIG_GPIO=n
 CONFIG_XIP=y
 
-# Workaround for incorect SYS_CLOCK_HW_CYCLES_PER_SEC
+# Workaround for incorrect SYS_CLOCK_HW_CYCLES_PER_SEC
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100

boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay

@@ -71,7 +71,7 @@
 	/*
 	 * All chip select pins have an on board 10k pull-up resistor to VCC,
 	 * and are connected to their respective arduino pins via a normally
-	 * closed solder brige.
+	 * closed solder bridge.
 	 *
 	 * All hold pins are connected to VCC with a 10k pull-up, and
 	 * have a connection to arduino pin A3 on CN8 via an open solder bridge.

boards/xtensa/intel_s1000_crb/support/device.py

@@ -7,7 +7,7 @@
 # Author: Sathish Kuttan <[email protected]>
 
 # This file defines device class that contains functions to
-# setup/cconfigure SPI master device and GPIO pins required
+# setup/configure SPI master device and GPIO pins required
 # to communicate with the target.
 # Member functions are provided to send and receive messages
 # over the SPI bus

cmake/bintools/bintools_template.cmake

@@ -10,7 +10,7 @@
 # - disassembly : Tool for disassemble the target
 # - elfconvert  : Tool for converting from elf into another format.
 # - readelf     : Tool for elf file processing
-# - strip       : Tool for symnbol stripping
+# - strip       : Tool for symbol stripping
 #
 # Each tool will have the following minimum properties:
 # - <tool>_command : Name of executable to call

cmake/bintools/host-gnu/target.cmake

@@ -5,7 +5,7 @@
 find_program(CMAKE_OBJCOPY objcopy)
 find_program(CMAKE_OBJDUMP objdump)
 find_program(CMAKE_AR      ar     )
-find_program(CMAKE_RANLILB ranlib )
+find_program(CMAKE_RANLIB  ranlib )
 find_program(CMAKE_READELF readelf)
 
 find_program(CMAKE_GDB     gdb    )

cmake/bintools/llvm/target.cmake

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-# Configures binary toos as llvm binary tool set
+# Configures binary tools as llvm binary tool set
 
 if(DEFINED TOOLCHAIN_HOME)
   set(find_program_clang_args PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH)

cmake/compiler/arcmwdt/compiler_flags.cmake

@@ -132,7 +132,7 @@ set_property(TARGET compiler-cpp PROPERTY dialect_cpp2a "")
 set_property(TARGET compiler-cpp PROPERTY dialect_cpp20 "")
 set_property(TARGET compiler-cpp PROPERTY dialect_cpp2b "")
 
-# Disable exeptions flag in C++
+# Disable exceptions flag in C++
 set_property(TARGET compiler-cpp PROPERTY no_exceptions "-fno-exceptions")
 
 # Disable rtti in C++

cmake/compiler/compiler_flags_template.cmake

@@ -65,7 +65,7 @@ set_property(TARGET compiler-cpp PROPERTY dialect_cpp2a)
 set_property(TARGET compiler-cpp PROPERTY dialect_cpp20)
 set_property(TARGET compiler-cpp PROPERTY dialect_cpp2b)
 
-# Flag for disabling exeptions in C++
+# Flag for disabling exceptions in C++
 set_property(TARGET compiler-cpp PROPERTY no_exceptions)
 
 # Flag for disabling rtti in C++