soc: rt11xx: Enable USDHC SD host controller on RT1170

Enable SD host controller driver for RT1170, so the EVK can use the new SD subsystem. Signed-off-by: Daniel DeGrasse <[email protected]>
benys · Apr 29, 2022 · a18338b · a18338b
1 parent aef290b
commit a18338b
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Showing 6 changed files with 20 additions and 21 deletions.
diff --git a/boards/arm/mimxrt1170_evk/Kconfig.defconfig b/boards/arm/mimxrt1170_evk/Kconfig.defconfig
@@ -19,12 +19,9 @@ if DISK_DRIVERS
 config DISK_DRIVER_SDMMC
 	default y
 
-config SDMMC_USDHC_DAT3_PWR_TOGGLE
+config IMX_USDHC_DAT3_PWR_TOGGLE
 	default y
 
-config SDMMC_USDHC_DAT3_PWR_DELAY
-	default 10
-
 endif # DISK_DRIVERS
 
 if FLASH

diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts
@@ -106,9 +106,13 @@
 
 &usdhc1 {
 	status = "okay";
-	no-1-8-v;
 	detect-dat3;
 	pwr-gpios = <&gpio10 2 GPIO_ACTIVE_LOW>;
+	mmc {
+		compatible = "zephyr,sdmmc-disk";
+		status = "okay";
+		label = "SDMMC_0";
+	};
 };
 
 &edma0 {

diff --git a/boards/arm/teensy4/Kconfig.defconfig b/boards/arm/teensy4/Kconfig.defconfig
@@ -21,14 +21,4 @@ endchoice
 config DISK_DRIVER_SDMMC
 	default y if DISK_DRIVERS
 
-if DISK_DRIVER_SDMMC
-
-config SDMMC_USDHC_DAT3_PWR_TOGGLE
-	default y
-
-config SDMMC_USDHC_DAT3_PWR_DELAY
-	default 10
-
-endif # DISK_DRIVER_SDMMC
-
 endif # BOARD_TEENSY40 || BOARD_TEENSY41
diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
@@ -55,7 +55,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 		break;
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC
 	case IMX_CCM_USDHC1_CLK:
 		clock_root = kCLOCK_Root_Usdhc1 + instance;
 		break;

diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi
@@ -775,21 +775,29 @@
 		};
 
 		usdhc1: usdhc@40418000 {
-			compatible = "nxp,imx-usdhc";
+			compatible = "nxp,imx-sdhc";
 			reg = <0x40418000 0x4000>;
 			status = "disabled";
 			interrupts = <133 0>;
 			clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
-			label = "USDHC_1";
+			label = "SDHC_0";
+			max-current-330 = <1020>;
+			max-current-180 = <1020>;
+			max-bus-freq = <208000000>;
+			min-bus-freq = <400000>;
 		};
 
 		usdhc2: usdhc@4041c000 {
-			compatible = "nxp,imx-usdhc";
+			compatible = "nxp,imx-sdhc";
 			reg = <0x4041c000 0x4000>;
 			status = "disabled";
 			interrupts = <134 0>;
 			clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
-			label = "USDHC_2";
+			label = "SDHC_1";
+			max-current-330 = <1020>;
+			max-current-180 = <1020>;
+			max-bus-freq = <208000000>;
+			min-bus-freq = <400000>;
 		};
 
 		csi: csi@40800000 {

diff --git a/soc/arm/nxp_imx/rt/soc_rt11xx.c b/soc/arm/nxp_imx/rt/soc_rt11xx.c
@@ -428,7 +428,7 @@ static ALWAYS_INLINE void clock_init(void)
 	USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig);
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC
 	/* Configure USDHC1 using  SysPll2Pfd2*/
 	rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2;
 	rootCfg.div = 2;