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drm/v3d: Set the correct DMA mask according to the MMU's limits.
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On 7278, we've got 40 bits to work with.

Signed-off-by: Eric Anholt <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Paul Kocialkowski <[email protected]>
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anholt committed May 16, 2019
1 parent 145986e commit 091d628
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Showing 3 changed files with 14 additions and 1 deletion.
1 change: 1 addition & 0 deletions drivers/gpu/drm/v3d/v3d_debugfs.c
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ static const struct v3d_reg_def v3d_hub_reg_defs[] = {
REGDEF(V3D_MMU_CTL),
REGDEF(V3D_MMU_VIO_ADDR),
REGDEF(V3D_MMU_VIO_ID),
REGDEF(V3D_MMU_DEBUG_INFO),
};

static const struct v3d_reg_def v3d_gca_reg_defs[] = {
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6 changes: 5 additions & 1 deletion drivers/gpu/drm/v3d/v3d_drv.c
Original file line number Diff line number Diff line change
Expand Up @@ -239,9 +239,9 @@ static int v3d_platform_drm_probe(struct platform_device *pdev)
struct drm_device *drm;
struct v3d_dev *v3d;
int ret;
u32 mmu_debug;
u32 ident1;

dev->coherent_dma_mask = DMA_BIT_MASK(36);

v3d = kzalloc(sizeof(*v3d), GFP_KERNEL);
if (!v3d)
Expand All @@ -258,6 +258,10 @@ static int v3d_platform_drm_probe(struct platform_device *pdev)
if (ret)
goto dev_free;

mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
dev->coherent_dma_mask =
DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));

ident1 = V3D_READ(V3D_HUB_IDENT1);
v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
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8 changes: 8 additions & 0 deletions drivers/gpu/drm/v3d/v3d_regs.h
Original file line number Diff line number Diff line change
Expand Up @@ -191,6 +191,14 @@
/* Address that faulted */
#define V3D_MMU_VIO_ADDR 0x01234

#define V3D_MMU_DEBUG_INFO 0x01238
# define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8)
# define V3D_MMU_PA_WIDTH_SHIFT 8
# define V3D_MMU_VA_WIDTH_MASK V3D_MASK(7, 4)
# define V3D_MMU_VA_WIDTH_SHIFT 4
# define V3D_MMU_VERSION_MASK V3D_MASK(3, 0)
# define V3D_MMU_VERSION_SHIFT 0

/* Per-V3D-core registers */

#define V3D_CTL_IDENT0 0x00000
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