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Prefix macros with VMM_ to reduce name clashes.
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@blitz
blitz committed Aug 13, 2013
1 parent bf4b2d1 commit e01f71c
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Showing 9 changed files with 178 additions and 178 deletions.
44 changes: 22 additions & 22 deletions executor/build_instructions.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -133,9 +133,9 @@ def generate_functions(name, flags, snippet, enc, functions, l2):
# Be sure to duplicate %s
snippet = ['asm volatile("'+ ";".join([re.sub(r'([^%])%([^%0-9])', r'\1%%\2', s) for s in snippet])+'" : "+d"(tmp_src), "+c"(tmp_dst) : : "eax")']
if "FPU" in flags:
if "FPUNORESTORE" not in flags: snippet = ['fxrstor (%%\" EXPAND(REG(ax)) \")'] + snippet
if "FPUNORESTORE" not in flags: snippet = ['fxrstor (%%\" VMM_EXPAND(VMM_REG(ax)) \")'] + snippet
snippet = ['if (cache->_cpu->cr0 & 0xc) EXCEPTION(cache, 0x7, 0)',
'asm volatile("' + ';'.join(snippet)+'; fxsave (%%\" EXPAND(REG(ax)) \");" : "+d"(tmp_src), "+c"(tmp_dst) : "a"(cache->_fpustate))']
'asm volatile("' + ';'.join(snippet)+'; fxsave (%%\" VMM_EXPAND(VMM_REG(ax)) \");" : "+d"(tmp_src), "+c"(tmp_dst) : "a"(cache->_fpustate))']
if "CPL0" in flags:
snippet = ["if (cache->cpl0_test()) return"] + snippet
# parameter handling
Expand Down Expand Up @@ -294,10 +294,10 @@ def print_code(code, functions):
("stc", ["NO_OS"], ["cache->_cpu->efl |= 1"]),
("cld", ["NO_OS"], ["cache->_cpu->efl &= ~0x400"]),
("std", ["NO_OS"], ["cache->_cpu->efl |= 0x400"]),
("bswap", ["NO_OS", "ASM"], ["mov (%\" EXPAND(REG(cx)) \"), %eax", "bswap %eax", "mov %eax, (%\" EXPAND(REG(cx)) \")"]),
("xchg", ["ASM", "RMW"], ["mov (%\" EXPAND(REG(dx)) \"), [EAX]", "[lock] xchg[bwl] [EAX], (%\" EXPAND(REG(cx)) \")", "mov [EAX], (%\" EXPAND(REG(dx)) \")"]),
("cwtl", ["ASM", "EAX"], ["mov (%\" EXPAND(REG(cx)) \"), [EAX]", "[data16] cwde", "mov [EAX], (%\" EXPAND(REG(cx)) \")"]),
("cltd", ["ASM", "EAX", "EDX", "DIRECTION"], ["mov (%\" EXPAND(REG(dx)) \"), %eax", "[data16] cltd", "mov %\" EXPAND(REG(dx)) \", (%\" EXPAND(REG(cx)) \")"]),
("bswap", ["NO_OS", "ASM"], ["mov (%\" VMM_EXPAND(VMM_REG(cx)) \"), %eax", "bswap %eax", "mov %eax, (%\" VMM_EXPAND(VMM_REG(cx)) \")"]),
("xchg", ["ASM", "RMW"], ["mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), [EAX]", "[lock] xchg[bwl] [EAX], (%\" VMM_EXPAND(VMM_REG(cx)) \")", "mov [EAX], (%\" VMM_EXPAND(VMM_REG(dx)) \")"]),
("cwtl", ["ASM", "EAX"], ["mov (%\" VMM_EXPAND(VMM_REG(cx)) \"), [EAX]", "[data16] cwde", "mov [EAX], (%\" VMM_EXPAND(VMM_REG(cx)) \")"]),
("cltd", ["ASM", "EAX", "EDX", "DIRECTION"], ["mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), %eax", "[data16] cltd", "mov %\" VMM_EXPAND(VMM_REG(dx)) \", (%\" VMM_EXPAND(VMM_REG(cx)) \")"]),
("str", ["NO_OS", "OS1"], ["move<1>(tmp_dst, &cache->_cpu->tr.sel)"]),
("sldt", ["NO_OS", "OS1"], ["move<1>(tmp_dst, &cache->_cpu->ld.sel)"]),
("smsw", ["NO_OS", "OS1"], ["move<1>(tmp_dst, &cache->_cpu->cr0)"]),
Expand All @@ -307,26 +307,26 @@ def print_code(code, functions):
("clflush", ["ASM", "BYTE"], [""]),
]
opcodes += [(x, ["ASM", "EAX", "NO_OS", x in ["aaa", "aas"] and "LOADFLAGS", "SAVEFLAGS"],
["#ifdef __x86_64__\n\tLogging::panic(\"Unable to execute '" + x + "'\\n\");\n#else\n\tasm volatile(\"mov (%%\" EXPAND(REG(cx)) \"), %%eax;" + x + ";mov %%eax, (%%\" EXPAND(REG(cx)) \")\" : \"+d\"(tmp_src), \"+c\"(tmp_dst) : : \"eax\");\n#endif\n"])
["#ifdef __x86_64__\n\tLogging::panic(\"Unable to execute '" + x + "'\\n\");\n#else\n\tasm volatile(\"mov (%%\" VMM_EXPAND(VMM_REG(cx)) \"), %%eax;" + x + ";mov %%eax, (%%\" VMM_EXPAND(VMM_REG(cx)) \")\" : \"+d\"(tmp_src), \"+c\"(tmp_dst) : : \"eax\");\n#endif\n"])
for x in ["aaa", "aas", "daa", "das"]]
opcodes += [(x, ["ASM", x in ["cmp", "test"] and "READONLY",
x in ["adc", "sbb"] and "LOADFLAGS",
x not in ["mov"] and "SAVEFLAGS",
x not in ["mov", "cmp", "test"] and "RMW",
],
["mov[bwl] (%\" EXPAND(REG(dx)) \"), [EAX]", "[lock] %s[bwl] [EAX],(%%\" EXPAND(REG(cx)) \")"%x])
["mov[bwl] (%\" VMM_EXPAND(VMM_REG(dx)) \"), [EAX]", "[lock] %s[bwl] [EAX],(%%\" VMM_EXPAND(VMM_REG(cx)) \")"%x])
for x in ["mov", "add", "adc", "sub", "sbb", "and", "or", "xor", "cmp", "test"]]
opcodes += [(x, ["ASM", x not in ["not"] and "SAVEFLAGS", x in ["dec", "inc"] and "LOADFLAGS", "RMW"],
["[lock] " + x + "[bwl] (%\" EXPAND(REG(cx)) \")"])
["[lock] " + x + "[bwl] (%\" VMM_EXPAND(VMM_REG(cx)) \")"])
for x in ["inc", "dec", "neg", "not"]]
opcodes += [(x, ["ASM", "CONST1", x in ["rcr", "rcl"] and "LOADFLAGS", "SAVEFLAGS", "RMW"],
["xchg %\" EXPAND(REG(dx)) \", %\" EXPAND(REG(cx)) \"","movb (%\" EXPAND(REG(cx)) \"),%cl", "%s[bwl] %%cl, (%%\" EXPAND(REG(dx)) \")"%x]) for x in ["rol", "ror", "rcl", "rcr", "shl", "shr", "sar"]]
opcodes += [(x, ["ASM", "SAVEFLAGS", "DIRECTION"], ["%s[bwl] (%%\" EXPAND(REG(dx)) \"), [EAX]"%x, "mov [EAX], (%\" EXPAND(REG(cx)) \")"]) for x in ["bsf", "bsr"]]
["xchg %\" VMM_EXPAND(VMM_REG(dx)) \", %\" VMM_EXPAND(VMM_REG(cx)) \"","movb (%\" VMM_EXPAND(VMM_REG(cx)) \"),%cl", "%s[bwl] %%cl, (%%\" VMM_EXPAND(VMM_REG(dx)) \")"%x]) for x in ["rol", "ror", "rcl", "rcr", "shl", "shr", "sar"]]
opcodes += [(x, ["ASM", "SAVEFLAGS", "DIRECTION"], ["%s[bwl] (%%\" VMM_EXPAND(VMM_REG(dx)) \"), [EAX]"%x, "mov [EAX], (%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["bsf", "bsr"]]
ccflags = map(lambda x: compile_and_disassemble(".byte %#x, 0x00"%x, file, fdict)[2].split()[0][1:], range(0x70, 0x80))
for i in range(len(ccflags)):
ccflag = ccflags[i]
opcodes += [("set" +ccflag, ["BYTE", "ASM", "LOADFLAGS"], ["set%s (%%\" EXPAND(REG(cx)) \")"%ccflag])]
opcodes += [("cmov"+ccflag, ["NO_OS", "ASM", "LOADFLAGS", "OS2"], ["j%s 1f"%(ccflags[i ^ 1]), "mov (%\" EXPAND(REG(dx)) \"), %eax", "mov %eax, (%\" EXPAND(REG(cx)) \")", "1:"])]
opcodes += [("set" +ccflag, ["BYTE", "ASM", "LOADFLAGS"], ["set%s (%%\" VMM_EXPAND(VMM_REG(cx)) \")"%ccflag])]
opcodes += [("cmov"+ccflag, ["NO_OS", "ASM", "LOADFLAGS", "OS2"], ["j%s 1f"%(ccflags[i ^ 1]), "mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), %eax", "mov %eax, (%\" VMM_EXPAND(VMM_REG(cx)) \")", "1:"])]
# use call %P0 instead of call %c0; seems to be a gcc-bug that occurs with -mcmodel=large
# (see http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46477)
opcodes += [("j"+ccflag, ["JMP", "ASM", "LOADFLAGS", "DIRECTION"],
Expand Down Expand Up @@ -379,7 +379,7 @@ def add_helper(l, flags, params):
"asm volatile (\"1: ;"
"%s[bwl] (%%2);"
"xor %%2, %%2;"
"2: ; .section .data.fixup2; \" ASM_WORD_TYPE \" 1b, 2b, 2b-1b; .previous;"
"2: ; .section .data.fixup2; \" VMM_ASM_WORD_TYPE \" 1b, 2b, 2b-1b; .previous;"
"\" : \"+a\"(eax), \"+d\"(edx), \"+c\"(tmp_src))"%x,
"if (tmp_src) DE0(cache)",
"cache->_cpu->eax = eax",
Expand All @@ -388,15 +388,15 @@ def add_helper(l, flags, params):
opcodes += [(x, ["RMW"], ["unsigned count",
"if ([IMM]) count = cache->_entry->immediate; else count = cache->_cpu->ecx",
"tmp_src = cache->get_reg32((cache->_entry->data[cache->_entry->offset_opcode] >> 3) & 0x7)",
'asm volatile ("xchg %%\" EXPAND(REG(ax)) \", %%\" EXPAND(REG(cx)) \"; mov (%%\" EXPAND(REG(dx)) \"), %%edx; [data16] '+
x+' %%cl, %%\" EXPAND(REG(dx)) \", (%%\" EXPAND(REG(ax)) \"); pushf; pop %%" EXPAND(REG(ax)) : "+a"(count), "+d"(tmp_src), "+c"(tmp_dst))',
'asm volatile ("xchg %%\" VMM_EXPAND(VMM_REG(ax)) \", %%\" VMM_EXPAND(VMM_REG(cx)) \"; mov (%%\" VMM_EXPAND(VMM_REG(dx)) \"), %%edx; [data16] '+
x+' %%cl, %%\" VMM_EXPAND(VMM_REG(dx)) \", (%%\" VMM_EXPAND(VMM_REG(ax)) \"); pushf; pop %%" VMM_EXPAND(VMM_REG(ax)) : "+a"(count), "+d"(tmp_src), "+c"(tmp_dst))',
"cache->_cpu->efl = (cache->_cpu->efl & ~0x8d5) | (count & 0x8d5)"])
for x in ["shrd", "shld"]]
opcodes += [("imul", ["DIRECTION"], ["unsigned param, result",
"tmp_dst = cache->get_reg32((cache->_entry->data[cache->_entry->offset_opcode] >> 3) & 0x7)",
"if ([IMM]) param = cache->_entry->immediate; else if ([OP1]) param = cache->_cpu->eax; else move<[os]>(&param, tmp_dst);",
# 'Logging::printf("IMUL %x * %x\\n", param, *reinterpret_cast<unsigned *>(tmp_src))',
'asm volatile ("imul[bwl] (%%\" EXPAND(REG(cx)) \"); pushf; pop %%" EXPAND(REG(cx)) : "+a"(param), "=d"(result), "+c"(tmp_src))',
'asm volatile ("imul[bwl] (%%\" VMM_EXPAND(VMM_REG(cx)) \"); pushf; pop %%" VMM_EXPAND(VMM_REG(cx)) : "+a"(param), "=d"(result), "+c"(tmp_src))',
"cache->_cpu->efl = (cache->_cpu->efl & ~0x8d5) | (reinterpret_cast<unsigned long>(tmp_src) & 0x8d5)",
"if ([OP1]) move<[os] ? [os] : 1>(&cache->_cpu->eax, &param)",
"if ([OP1] && [os]) move<[os]>(&cache->_cpu->edx, &result)",
Expand All @@ -422,17 +422,17 @@ def add_helper(l, flags, params):
("pop %"+x, [], ["unsigned sel", "cache->helper_POP<[os]>(&sel) || cache->set_segment(&cache->_cpu->%s, sel)"%x, x == "ss" and "cache->_cpu->intr_state |= 2" or ""]),
("l"+x, ["SKIPMODRM", "MODRM", "MEMONLY"], ["cache->helper_loadsegment<[os]>(&cache->_cpu->%s)"%x])]
opcodes += [(x, ["FPU", "FPUNORESTORE", "NO_OS"], [x]) for x in ["fninit"]]
opcodes += [(x, ["FPU", "NO_OS"], [x+" (%%\" EXPAND(REG(cx)) \")"]) for x in ["fnstsw", "fnstcw", "ficom", "ficomp"]]
opcodes += [(x, ["FPU", "NO_OS", "EAX"], ["fnstsw (%%\" EXPAND(REG(cx)) \")"]) for x in ["fnstsw %ax"]]
opcodes += [(x, ["FPU", "NO_OS"], [x+" (%%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["fnstsw", "fnstcw", "ficom", "ficomp"]]
opcodes += [(x, ["FPU", "NO_OS", "EAX"], ["fnstsw (%%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["fnstsw %ax"]]
opcodes += [(".byte 0xdb, 0xe4 ", ["NO_OS", "COMPLETE"], ["/* fnsetpm, on 287 only, noop afterwards */"])]
opcodes += [(x, [x not in ["bt"] and "RMW" or "READONLY", "SAVEFLAGS", "BITS", "ASM"], ["mov (%\" EXPAND(REG(dx)) \"), %eax",
opcodes += [(x, [x not in ["bt"] and "RMW" or "READONLY", "SAVEFLAGS", "BITS", "ASM"], ["mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), %eax",
"and $(8<<[os])-1, %eax",
"[lock] "+x+" [EAX],(%\" EXPAND(REG(cx)) \")"]) for x in ["bt", "btc", "bts", "btr"]]
"[lock] "+x+" [EAX],(%\" VMM_EXPAND(VMM_REG(cx)) \")"]) for x in ["bt", "btc", "bts", "btr"]]
opcodes += [("cmpxchg", ["RMW"], ['char res; asm volatile("mov (%2), %2; [lock] cmpxchg [EDX], (%3); setz %1" : "+a"(cache->_cpu->eax), "=d"(res) : "d"(tmp_src), "c"(tmp_dst))',
"if (res) cache->_cpu->efl |= EFL_ZF; else cache->_cpu->efl &= EFL_ZF"])]
opcodes += [("cmpxchg8b", ["RMW", "NO_OS", "QWORD"], ['char res; asm volatile("[lock] cmpxchg8b (%3); setz %2" : "+a"(cache->_cpu->eax), "+d"(cache->_cpu->edx), "=c"(res) : "D"(tmp_dst), "b"(cache->_cpu->ebx), "c"(cache->_cpu->ecx))',
"if (res) cache->_cpu->efl |= EFL_ZF; else cache->_cpu->efl &= EFL_ZF"])]
opcodes += [("xadd", ["RMW", "ASM", "SAVEFLAGS"], ['mov (%\" EXPAND(REG(dx)) \"), [EAX]', '[lock] xadd [EAX], (%\" EXPAND(REG(cx)) \")', 'mov [EAX], (%\" EXPAND(REG(dx)) \")'])]
opcodes += [("xadd", ["RMW", "ASM", "SAVEFLAGS"], ['mov (%\" VMM_EXPAND(VMM_REG(dx)) \"), [EAX]', '[lock] xadd [EAX], (%\" VMM_EXPAND(VMM_REG(cx)) \")', 'mov [EAX], (%\" VMM_EXPAND(VMM_REG(dx)) \")'])]

# unimplemented instructions
opcodes += [(x, [], []) for x in ["vmcall", "vmlaunch", "vmresume", "vmxoff", "vmptrld", "vmptrst", "vmread", "vmwrite"]] # , "vmxon", "vmclear"
Expand Down
12 changes: 6 additions & 6 deletions executor/instcache.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,15 +18,15 @@
#pragma once

#ifdef __i386__
#define REG(X) e ## X
#define ASM_WORD_TYPE ".long"
#define VMM_REG(X) e ## X
#define VMM_ASM_WORD_TYPE ".long"
#else
#define REG(X) r ## X
#define ASM_WORD_TYPE ".quad"
#define VMM_REG(X) r ## X
#define VMM_ASM_WORD_TYPE ".quad"
#endif

#define STRING(x) # x
#define EXPAND(x) STRING(x)
#define VMM_STRING(x) # x
#define VMM_EXPAND(x) VMM_STRING(x)

/**
* Reverse MTR mapping.
Expand Down
66 changes: 33 additions & 33 deletions include/model/reg.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,44 +15,44 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License version 2 for more details.
*/
#define DEFINE_REG(NAME, OFFSET, VALUE, MASK) private: unsigned NAME; public: static const unsigned NAME##_offset = OFFSET; static const unsigned NAME##_mask = MASK; static const unsigned NAME##_reset = VALUE;
#define REG_RO(NAME, OFFSET, VALUE) REG(NAME, OFFSET, static const unsigned NAME = VALUE;, value = VALUE; , break; , )
#define REG_RW(NAME, OFFSET, VALUE, MASK, WRITE_CALLBACK) REG(NAME, OFFSET, DEFINE_REG(NAME, OFFSET, VALUE, MASK) , value = NAME; , if (!MASK) return false; if (strict && value & ~MASK) return false; NAME = (NAME & ~MASK) | (value & MASK); WRITE_CALLBACK; , NAME=VALUE;)
#define REG_WR(NAME, OFFSET, VALUE, MASK, RW1S, RW1C, WRITE_CALLBACK) REG(NAME, OFFSET, DEFINE_REG(NAME, OFFSET, VALUE, MASK), value = NAME; , if (!MASK) return false; unsigned oldvalue = NAME; value = value & ~RW1S | ( value | oldvalue) & RW1S; value = value & ~RW1C | (~value & oldvalue) & RW1C; NAME = (NAME & ~MASK) | (value & MASK); WRITE_CALLBACK; , NAME = VALUE;)
#define REGSET(NAME, ...) private: __VA_ARGS__
#define REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) MEMBER
#include REGBASE
#undef REG
#undef REGSET
#define REGSET(NAME, ...) bool NAME##_read(unsigned offset, unsigned &value) { switch (offset) { __VA_ARGS__ default: break; } return false; }
#define REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) case OFFSET: { READ }; return true;
#include REGBASE
#undef REG
#undef REGSET
#define REGSET(NAME, ...) bool NAME##_write(unsigned offset, unsigned value, bool strict=false) { switch (offset) { __VA_ARGS__ default: break; } return 0; }
#define REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) case OFFSET: { WRITE }; return true;
#include REGBASE
#undef REG
#undef REGSET
#define REGSET(NAME, ...) void NAME##_reset() { __VA_ARGS__ }; private:
#define REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) RESET
#include REGBASE
#undef REG
#undef REGSET
#undef REG_WR
#undef REG_RW
#undef REG_RO
#undef DEFINE_REG
#undef REGBASE
#define VMM_DEFINE_REG(NAME, OFFSET, VALUE, MASK) private: unsigned NAME; public: static const unsigned NAME##_offset = OFFSET; static const unsigned NAME##_mask = MASK; static const unsigned NAME##_reset = VALUE;
#define VMM_REG_RO(NAME, OFFSET, VALUE) VMM_REG(NAME, OFFSET, static const unsigned NAME = VALUE;, value = VALUE; , break; , )
#define VMM_REG_RW(NAME, OFFSET, VALUE, MASK, WRITE_CALLBACK) VMM_REG(NAME, OFFSET, VMM_DEFINE_REG(NAME, OFFSET, VALUE, MASK) , value = NAME; , if (!MASK) return false; if (strict && value & ~MASK) return false; NAME = (NAME & ~MASK) | (value & MASK); WRITE_CALLBACK; , NAME=VALUE;)
#define VMM_REG_WR(NAME, OFFSET, VALUE, MASK, RW1S, RW1C, WRITE_CALLBACK) VMM_REG(NAME, OFFSET, VMM_DEFINE_REG(NAME, OFFSET, VALUE, MASK), value = NAME; , if (!MASK) return false; unsigned oldvalue = NAME; value = value & ~RW1S | ( value | oldvalue) & RW1S; value = value & ~RW1C | (~value & oldvalue) & RW1C; NAME = (NAME & ~MASK) | (value & MASK); WRITE_CALLBACK; , NAME = VALUE;)
#define VMM_REGSET(NAME, ...) private: __VA_ARGS__
#define VMM_REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) MEMBER
#include VMM_REGBASE
#undef VMM_REG
#undef VMM_REGSET
#define VMM_REGSET(NAME, ...) bool NAME##_read(unsigned offset, unsigned &value) { switch (offset) { __VA_ARGS__ default: break; } return false; }
#define VMM_REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) case OFFSET: { READ }; return true;
#include VMM_REGBASE
#undef VMM_REG
#undef VMM_REGSET
#define VMM_REGSET(NAME, ...) bool NAME##_write(unsigned offset, unsigned value, bool strict=false) { switch (offset) { __VA_ARGS__ default: break; } return 0; }
#define VMM_REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) case OFFSET: { WRITE }; return true;
#include VMM_REGBASE
#undef VMM_REG
#undef VMM_REGSET
#define VMM_REGSET(NAME, ...) void NAME##_reset() { __VA_ARGS__ }; private:
#define VMM_REG(NAME, OFFSET, MEMBER, READ, WRITE, RESET) RESET
#include VMM_REGBASE
#undef VMM_REG
#undef VMM_REGSET
#undef VMM_REG_WR
#undef VMM_REG_RW
#undef VMM_REG_RO
#undef VMM_DEFINE_REG
#undef VMM_REGBASE

/**
* \def REG_RO(NAME, OFFSET, VALUE)
* \def VMM_REG_RO(NAME, OFFSET, VALUE)
*
* Defines a read-only register.
*/

/**
* \def REG_RW(NAME, OFFSET, VALUE, MASK, WRITE_CALLBACK)
* \def VMM_REG_RW(NAME, OFFSET, VALUE, MASK, WRITE_CALLBACK)
*
* Defines a read/write register.
*
Expand All @@ -64,7 +64,7 @@
*/

/**
* \def REG_WR(NAME, OFFSET, VALUE, MASK, RW1S, RW1C, WRITE_CALLBACK)
* \def VMM_REG_WR(NAME, OFFSET, VALUE, MASK, RW1S, RW1C, WRITE_CALLBACK)
*
* Defines a read/write register with set/clear bits.
*
Expand All @@ -78,7 +78,7 @@
*/

/**
* \def REGSET(NAME, ...)
* \def VMM_REGSET(NAME, ...)
*
* Defines a set of registers.
*/
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