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Pull requests: bluespec/Piccolo
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PLIC: Allow multiple interrupts to be claimed but not completed
#39
by jrtc27
was merged Mar 12, 2021
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Added check for NaN on output of FP compute pipelines
#22
by nirajnsharma
was merged Dec 3, 2019
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CSR_RegFile_MSU.bsv: Legalise PC on SRET as with MRET
#21
by jrtc27
was merged Oct 30, 2019
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Add constraints to Xilinx IP project for the internal JTAG clock
#14
by dhand-galois
was merged Feb 5, 2019
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Update the Xilinx IP packaging for the SSITH P1 to include the WID ports
#13
by quark17
was merged Feb 1, 2019
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Fix the SoC reset so that it can be called more than once
#7
by quark17
was merged Nov 29, 2018
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In the trace encoder, fix the generation of the group for memory writes.
#5
by quark17
was merged Nov 21, 2018
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Fixes to compile without ISA_PRIV_S and to interoperate with other BRVF_Core versions
#4
by quark17
was merged Nov 9, 2018
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Fixes to get code to compile with different macro definitions than usual
#3
by quark17
was merged Nov 6, 2018
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