Skip to content
View boksop's full-sized avatar

Block or report boksop

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

iCESugar FPGA Board (base on iCE40UP5k)

Verilog 371 97 Updated Nov 4, 2024

MXM to PCIe adapter

38 5 Updated Dec 17, 2024

Volumetric Display using an Acoustically Trapped Particle

Verilog 461 48 Updated Nov 26, 2024

Reverse engineering of the Quansheng UV-K5 V1.4 PCB in KiCad 7

322 69 Updated Oct 31, 2024

KitProg3 Firmware repo

C 14 2 Updated Dec 5, 2024

100kHz to 6GHz 2 port USB based VNA

C++ 1,207 221 Updated Feb 14, 2025

Book_1_《编程不难》 | 鸢尾花书:从加减乘除到机器学习;请多多批评指正!

Jupyter Notebook 5,294 1,038 Updated Sep 11, 2024

A FPGA friendly 32 bit RISC-V CPU implementation

Assembly 2,660 427 Updated Feb 14, 2025

image processing based FPGA

VHDL 100 27 Updated Sep 2, 2021

手搓CPU系列-硬件设计

11 4 Updated Mar 21, 2023

3-phase motor controller with integrated position sensor

PLSQL 542 220 Updated Oct 28, 2021

国产VU13P加速卡资料

C 61 17 Updated Jan 22, 2025

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

SystemVerilog 234 73 Updated Feb 14, 2025

一个低成本大型全套四足机器人软硬件开源项目

Python 954 205 Updated Apr 11, 2022

中文版 Parallel Programming for FPGAs

CSS 719 159 Updated Aug 21, 2024

帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目

4,328 705 Updated May 15, 2022

🐋蓝鲸直播源-长期维护的电视直播源接口、TVBox、Pluto Player、猫影视TV、IPTV、BIUBIU TV、IPTV源、直播源、源享家、蓝鲸直播源、等影视及m3u8播放器通用接口都可观看

4,864 509 Updated Jan 26, 2025

DisplayPort IP-core

Verilog 61 10 Updated Feb 11, 2025

Build your hardware, easily!

C 3,152 591 Updated Feb 14, 2025

Tools for plotting an eye diagram in Python.

Python 48 23 Updated Jun 16, 2023

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Assembly 2,373 721 Updated Feb 13, 2025

Vendor and platform neutral SDR support library.

C++ 1,193 185 Updated Dec 21, 2024

Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7

Shell 65 8 Updated Jun 21, 2024

PCB for ULX3S FPGA R&D board

OpenSCAD 381 65 Updated Jul 30, 2023

A minimal, modularized, and machine-independent hardware abstraction layer

C 468 89 Updated Dec 29, 2024

Yosys Open SYnthesis Suite

C++ 3,637 908 Updated Feb 15, 2025

nextpnr portable FPGA place and route tool

C++ 1,381 250 Updated Feb 14, 2025

current focus on Colorlight i5 and i9 & i9plus module

Verilog 280 62 Updated Oct 6, 2024

A Verilog implementation of DisplayPort protocol for FPGAs

Verilog 242 52 Updated Mar 15, 2019
SystemVerilog 18 1 Updated Nov 7, 2019
Next