MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT

Commit 930beb5 ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non coherent DMA because of a wrong allocation alignment. Fixes: 930beb5 ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") Signed-off-by: Thomas Bogendoerfer <[email protected]>
boxfire · Sep 15, 2020 · 564c836 · 564c836
1 parent baf5cb3
commit 564c836
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
@@ -877,6 +877,7 @@ config SNI_RM
 	select I8253
 	select I8259
 	select ISA
+	select MIPS_L1_CACHE_SHIFT_6
 	select SWAP_IO_SPACE if CPU_BIG_ENDIAN
 	select SYS_HAS_CPU_R4X00
 	select SYS_HAS_CPU_R5000