hardware implementation of histogram equalization / matching in chisel

A python script for randomly generating DAGs

This is a set of stricts for comparing the area performance of semi-aligned and fully aligned; load store and non load store memory architectures.

This is a Python wrapper for Xilinx ISE with the added functionality of batch synthesis and simulation. The console output of batch operations are logged.

Qt application simulating an FPGA board with digits, leds, buttons and switches

Reverse image search accelerated using a FPGA

Creates a state diagram from the given Verilog file

Password manager application