pulley: Implement getting the link register (#9720)

Fill out `get_return_address` lowering in Cranelift.
bytecodealliance · Dec 3, 2024 · db95666 · db95666
1 parent 75a4d27
commit db95666
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Showing 7 changed files with 83 additions and 4 deletions.
diff --git a/cranelift/codegen/src/isa/pulley_shared/abi.rs b/cranelift/codegen/src/isa/pulley_shared/abi.rs
@@ -296,7 +296,7 @@ where
             insts.push(
                 Inst::gen_store(
                     Amode::SpOffset { offset: 8 },
-                    link_reg(),
+                    lr_reg(),
                     I64,
                     MemFlags::trusted(),
                 )
@@ -345,7 +345,7 @@ where
         if frame_layout.setup_area_size > 0 {
             insts.push(
                 Inst::gen_load(
-                    writable_link_reg(),
+                    writable_lr_reg(),
                     Amode::SpOffset { offset: 8 },
                     I64,
                     MemFlags::trusted(),
@@ -405,7 +405,7 @@ where
                 insts.push(
                     Inst::gen_store(
                         Amode::SpOffset { offset: 8 },
-                        link_reg(),
+                        lr_reg(),
                         I64,
                         MemFlags::trusted(),
                     )

diff --git a/cranelift/codegen/src/isa/pulley_shared/inst.isle b/cranelift/codegen/src/isa/pulley_shared/inst.isle
@@ -387,6 +387,9 @@
 (decl fp_reg () XReg)
 (extern constructor fp_reg fp_reg)
 
+(decl lr_reg () XReg)
+(extern constructor lr_reg lr_reg)
+
 (decl pulley_get_special (XReg) XReg)
 (rule (pulley_get_special reg)
       (let ((dst WritableXReg (temp_writable_xreg))

diff --git a/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs b/cranelift/codegen/src/isa/pulley_shared/inst/regs.rs
@@ -91,7 +91,7 @@ define_registers! {
     x_reg(26) => x26, writable_x26;
 
     x_reg(27) => stack_reg, writable_stack_reg;
-    x_reg(28) => link_reg, writable_link_reg;
+    x_reg(28) => lr_reg, writable_lr_reg;
     x_reg(29) => fp_reg, writable_fp_reg;
     x_reg(30) => spilltmp_reg, writable_spilltmp_reg;
     x_reg(31) => spilltmp2_reg, writable_spilltmp2_reg;

diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.isle b/cranelift/codegen/src/isa/pulley_shared/lower.isle
@@ -121,6 +121,11 @@
 (rule (lower (get_frame_pointer))
       (pulley_get_special (fp_reg)))
 
+;;;; Rules for `get_return_address` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (get_return_address))
+      (pulley_get_special (lr_reg)))
+
 ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; N.B.: the `ret` itself is generated by the ABI.

diff --git a/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs b/cranelift/codegen/src/isa/pulley_shared/lower/isle.rs
@@ -110,6 +110,10 @@ where
     fn fp_reg(&mut self) -> XReg {
         XReg::new(regs::fp_reg()).unwrap()
     }
+
+    fn lr_reg(&mut self) -> XReg {
+        XReg::new(regs::lr_reg()).unwrap()
+    }
 }
 
 /// The main entry point for lowering with ISLE.

diff --git a/cranelift/filetests/filetests/isa/pulley32/special_regs.clif b/cranelift/filetests/filetests/isa/pulley32/special_regs.clif
@@ -68,3 +68,36 @@ block0:
 ; xadd32 sp, sp, spilltmp0
 ; ret
 
+function %get_return_address() -> i32 {
+block0:
+  v0 = get_return_address.i32
+  return v0
+}
+
+; VCode:
+;   x30 = xconst8 -16
+;   x27 = xadd32 x27, x30
+;   store64 sp+8, x28 // flags =  notrap aligned
+;   store64 sp+0, x29 // flags =  notrap aligned
+;   x29 = xmov x27
+; block0:
+;   xmov x0, x28
+;   x28 = load64_u sp+8 // flags = notrap aligned
+;   x29 = load64_u sp+0 // flags = notrap aligned
+;   x30 = xconst8 16
+;   x27 = xadd32 x27, x30
+;   ret
+;
+; Disassembled:
+; xconst8 spilltmp0, -16
+; xadd32 sp, sp, spilltmp0
+; store64_offset8 sp, 8, lr
+; store64 sp, fp
+; xmov fp, sp
+; xmov x0, lr
+; load64_offset8 lr, sp, 8
+; load64 fp, sp
+; xconst8 spilltmp0, 16
+; xadd32 sp, sp, spilltmp0
+; ret
+
diff --git a/cranelift/filetests/filetests/isa/pulley64/special_regs.clif b/cranelift/filetests/filetests/isa/pulley64/special_regs.clif
@@ -68,3 +68,37 @@ block0:
 ; xadd32 sp, sp, spilltmp0
 ; ret
 
+
+function %get_return_address() -> i64 {
+block0:
+  v0 = get_return_address.i64
+  return v0
+}
+
+; VCode:
+;   x30 = xconst8 -16
+;   x27 = xadd32 x27, x30
+;   store64 sp+8, x28 // flags =  notrap aligned
+;   store64 sp+0, x29 // flags =  notrap aligned
+;   x29 = xmov x27
+; block0:
+;   xmov x0, x28
+;   x28 = load64_u sp+8 // flags = notrap aligned
+;   x29 = load64_u sp+0 // flags = notrap aligned
+;   x30 = xconst8 16
+;   x27 = xadd32 x27, x30
+;   ret
+;
+; Disassembled:
+; xconst8 spilltmp0, -16
+; xadd32 sp, sp, spilltmp0
+; store64_offset8 sp, 8, lr
+; store64 sp, fp
+; xmov fp, sp
+; xmov x0, lr
+; load64_offset8 lr, sp, 8
+; load64 fp, sp
+; xconst8 spilltmp0, 16
+; xadd32 sp, sp, spilltmp0
+; ret
+