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MIPS: Fix R2300 FP context switch handling
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Commit 1a3d595 ("MIPS: Tidy up FPU context switching") removed FP
context saving from the asm-written resume function in favour of reusing
existing code to perform the same task. However it only removed the FP
context saving code from the r4k_switch.S implementation of resume.
Remove it from the r2300_switch.S implementation too in order to prevent
attempting to save the FP context twice, which would likely lead to an
exception from the second save because the FPU had already been disabled
by the first save.

This patch has only been build tested, using rbtx49xx_defconfig.

Fixes: 1a3d595 ("MIPS: Tidy up FPU context switching")
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Cc: Manuel Lauss <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/11167/
Signed-off-by: Ralf Baechle <[email protected]>
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paulburton authored and ralfbaechle committed Oct 2, 2015
1 parent 0fa2434 commit 085c2f2
Showing 1 changed file with 1 addition and 27 deletions.
28 changes: 1 addition & 27 deletions arch/mips/kernel/r2300_switch.S
Original file line number Diff line number Diff line change
Expand Up @@ -30,42 +30,16 @@
*/
#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)

/*
* FPU context is saved iff the process has used it's FPU in the current
* time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user
* space STATUS register should be 0, so that a process *always* starts its
* userland with FPU disabled after each context switch.
*
* FPU will be enabled as soon as the process accesses FPU again, through
* do_cpu() trap.
*/

/*
* task_struct *resume(task_struct *prev, task_struct *next,
* struct thread_info *next_ti, int usedfpu)
* struct thread_info *next_ti)
*/
LEAF(resume)
mfc0 t1, CP0_STATUS
sw t1, THREAD_STATUS(a0)
cpu_save_nonscratch a0
sw ra, THREAD_REG31(a0)

beqz a3, 1f

PTR_L t3, TASK_THREAD_INFO(a0)

/*
* clear saved user stack CU1 bit
*/
lw t0, ST_OFF(t3)
li t1, ~ST0_CU1
and t0, t0, t1
sw t0, ST_OFF(t3)

fpu_save_single a0, t0 # clobbers t0

1:

#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
PTR_LA t8, __stack_chk_guard
LONG_L t9, TASK_STACK_CANARY(a1)
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