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MIPS: Octeon: Guard the Kconfig body with CPU_CAVIUM_OCTEON
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Instead of making each Octeon specific option depend on
CPU_CAVIUM_OCTEON, gate the body of the entire file with
CPU_CAVIUM_OCTEON.  With this change, CAVIUM_OCTEON_SPECIFIC_OPTIONS
becomes useless, so get rid of it as well.

Signed-off-by: David Daney <[email protected]>
To: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/2091/
Signed-off-by: Ralf Baechle <[email protected]>
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David Daney authored and ralfbaechle committed May 10, 2011
1 parent e3fb3f2 commit 23a271e
Showing 1 changed file with 4 additions and 11 deletions.
15 changes: 4 additions & 11 deletions arch/mips/cavium-octeon/Kconfig
Original file line number Diff line number Diff line change
@@ -1,11 +1,7 @@
config CAVIUM_OCTEON_SPECIFIC_OPTIONS
bool "Enable Octeon specific options"
depends on CPU_CAVIUM_OCTEON
default "y"
if CPU_CAVIUM_OCTEON

config CAVIUM_CN63XXP1
bool "Enable CN63XXP1 errata worarounds"
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
default "n"
help
The CN63XXP1 chip requires build time workarounds to
Expand All @@ -16,7 +12,6 @@ config CAVIUM_CN63XXP1

config CAVIUM_OCTEON_2ND_KERNEL
bool "Build the kernel to be used as a 2nd kernel on the same chip"
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
default "n"
help
This option configures this kernel to be linked at a different
Expand All @@ -26,7 +21,6 @@ config CAVIUM_OCTEON_2ND_KERNEL

config CAVIUM_OCTEON_HW_FIX_UNALIGNED
bool "Enable hardware fixups of unaligned loads and stores"
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
default "y"
help
Configure the Octeon hardware to automatically fix unaligned loads
Expand All @@ -38,7 +32,6 @@ config CAVIUM_OCTEON_HW_FIX_UNALIGNED

config CAVIUM_OCTEON_CVMSEG_SIZE
int "Number of L1 cache lines reserved for CVMSEG memory"
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
range 0 54
default 1
help
Expand All @@ -50,7 +43,6 @@ config CAVIUM_OCTEON_CVMSEG_SIZE

config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
default "y"
help
Enable locking parts of the kernel into the L2 cache.
Expand Down Expand Up @@ -93,7 +85,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY
config ARCH_SPARSEMEM_ENABLE
def_bool y
select SPARSEMEM_STATIC
depends on CPU_CAVIUM_OCTEON

config CAVIUM_OCTEON_HELPER
def_bool y
Expand All @@ -107,6 +98,8 @@ config NEED_SG_DMA_LENGTH

config SWIOTLB
def_bool y
depends on CPU_CAVIUM_OCTEON
select IOMMU_HELPER
select NEED_SG_DMA_LENGTH


endif # CPU_CAVIUM_OCTEON

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