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s3c-fb: correct FRAMESEL1 bitfield defines for VIDINTCON0 register
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FRAMESEL1 bitfield starts on 13th bit, not on 14th.

Signed-off-by: Pawel Osciak <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Acked-by: Ben Dooks <[email protected]>
Cc: InKi Dae <[email protected]>
Cc: Marek Szyprowski <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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Pawel Osciak authored and torvalds committed Aug 11, 2010
1 parent cd7d7e0 commit 9fa424a
Showing 1 changed file with 5 additions and 5 deletions.
10 changes: 5 additions & 5 deletions arch/arm/plat-samsung/include/plat/regs-fb.h
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Original file line number Diff line number Diff line change
Expand Up @@ -292,11 +292,11 @@
#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)

#define VIDINTCON0_FRAMESEL1 (1 << 14)
#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14)
#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14)
#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14)
#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14)
#define VIDINTCON0_FRAMESEL1 (1 << 13)
#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)

#define VIDINTCON0_INT_FRAME (1 << 12)
#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
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