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ARM: add base support for Marvell Dove SoC
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The Marvell Dove (88AP510) is a high-performance, highly integrated,
low power SoC with high-end ARM-compatible processor (known as PJ4),
graphics processing unit, high-definition video decoding acceleration
hardware, and a broad range of peripherals.

Signed-off-by: Lennert Buytenhek <[email protected]>
Signed-off-by: Saeed Bishara <[email protected]>
Signed-off-by: Nicolas Pitre <[email protected]>
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@npitre
Saeed Bishara authored and npitre committed Nov 27, 2009
1 parent 8d27b2f commit edabd38
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Showing 29 changed files with 3,773 additions and 2 deletions.
13 changes: 13 additions & 0 deletions arch/arm/Kconfig
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Expand Up @@ -433,6 +433,17 @@ config ARCH_L7200
If you have any questions or comments about the Linux kernel port
to this board, send e-mail to <[email protected]>.

config ARCH_DOVE
bool "Marvell Dove"
select PCI
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select PLAT_ORION
help
Support for the Marvell Dove SoC 88AP510

config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
select CPU_FEROCEON
Expand Down Expand Up @@ -747,6 +758,8 @@ source "arch/arm/mach-orion5x/Kconfig"

source "arch/arm/mach-kirkwood/Kconfig"

source "arch/arm/mach-dove/Kconfig"

source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c64xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
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1 change: 1 addition & 0 deletions arch/arm/Makefile
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Expand Up @@ -122,6 +122,7 @@ machine-$(CONFIG_ARCH_AT91) := at91
machine-$(CONFIG_ARCH_BCMRING) := bcmring
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_DAVINCI) := davinci
machine-$(CONFIG_ARCH_DOVE) := dove
machine-$(CONFIG_ARCH_EBSA110) := ebsa110
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
machine-$(CONFIG_ARCH_GEMINI) := gemini
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6 changes: 6 additions & 0 deletions arch/arm/boot/compressed/head.S
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Expand Up @@ -743,6 +743,12 @@ proc_types:
W(b) __armv4_mmu_cache_off
W(b) __armv6_mmu_cache_flush

.word 0x560f5810 @ Marvell PJ4 ARMv6
.word 0xff0ffff0
W(b) __armv4_mmu_cache_on
W(b) __armv4_mmu_cache_off
W(b) __armv6_mmu_cache_flush

.word 0x000f0000 @ new CPU Id
.word 0x000f0000
W(b) __armv7_mmu_cache_on
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