platform: msm_shared: Cleanup mdp5 pipe select and flush code

1) Cleanup code repetition for pipe selection and flush using static functions. 2) Move pipe and mixer base address to target ipmap header file. 3) Combine switch cases for left and right pipes. Change-Id: I1bda342dfab652742a207a3f934d9271a02e9e76
cbrown1 · May 29, 2014 · 0737392 · 0737392
1 parent a59cc9d
commit 0737392
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Showing 6 changed files with 98 additions and 159 deletions.
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
@@ -213,21 +213,6 @@
 #define BOOT_CONFIG_OFFSET          0x00006034
 #define BOOT_CONFIG_REG             (SEC_CTRL_CORE_BASE+BOOT_CONFIG_OFFSET)
 
-/* mdss */
-#define MSM_MMSS_CLK_CTL_BASE       0xFD8C0000
-
-#define MIPI_DSI_BASE               (0xFD922800)
-#define MIPI_DSI0_BASE              (MIPI_DSI_BASE)
-#define MIPI_DSI1_BASE              (0xFD922E00)
-#define DSI0_PHY_BASE               (0xFD922B00)
-#define DSI1_PHY_BASE               (0xFD923100)
-#define DSI0_PLL_BASE               (0xFD922A00)
-#define DSI1_PLL_BASE               (0xFD923000)
-#define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
-
-#define MDP_BASE                    (0xfd900000)
-#define REG_MDP(off)                (MDP_BASE + (off))
-
 #define SOFT_RESET                  0x118
 #define CLK_CTRL                    0x11C
 #define TRIG_CTRL                   0x084
@@ -251,6 +236,18 @@
 #define VIDEO_MODE_VSYNC            0x034
 #define VIDEO_MODE_VSYNC_VPOS       0x038
 
+/* MDSS */
+#define MSM_MMSS_CLK_CTL_BASE       0xFD8C0000
+#define MIPI_DSI_BASE               (0xFD922800)
+#define MIPI_DSI0_BASE              (MIPI_DSI_BASE)
+#define MIPI_DSI1_BASE              (0xFD922E00)
+#define DSI0_PHY_BASE               (0xFD922B00)
+#define DSI1_PHY_BASE               (0xFD923100)
+#define DSI0_PLL_BASE               (0xFD922A00)
+#define DSI1_PLL_BASE               (0xFD923000)
+#define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
+#define MDP_BASE                    (0xfd900000)
+#define REG_MDP(off)                (MDP_BASE + (off))
 #define MDP_VP_0_VIG_0_BASE         REG_MDP(0x1200)
 #define MDP_VP_0_VIG_1_BASE         REG_MDP(0x1600)
 #define MDP_VP_0_RGB_0_BASE         REG_MDP(0x2200)

diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
@@ -179,6 +179,14 @@
 #define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
 #define MDP_BASE                    (0xfd900000)
 #define REG_MDP(off)                (MDP_BASE + (off))
+#define MDP_VP_0_VIG_0_BASE          REG_MDP(0x1200)
+#define MDP_VP_0_VIG_1_BASE          REG_MDP(0x1600)
+#define MDP_VP_0_RGB_0_BASE          REG_MDP(0x1E00)
+#define MDP_VP_0_RGB_1_BASE          REG_MDP(0x2200)
+#define MDP_VP_0_DMA_0_BASE          REG_MDP(0x2A00)
+#define MDP_VP_0_DMA_1_BASE          REG_MDP(0x2E00)
+#define MDP_VP_0_MIXER_0_BASE        REG_MDP(0x3200)
+#define MDP_VP_0_MIXER_1_BASE        REG_MDP(0x3600)
 
 #define SOFT_RESET                  0x118
 #define CLK_CTRL                    0x11C

diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
@@ -144,15 +144,17 @@
 #define DSI0_PLL_BASE               (0x1A98300)
 #define DSI1_PLL_BASE               DSI0_PLL_BASE
 #define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
-
 #define MDP_BASE                    (0x1A00000)
 #define REG_MDP(off)                (MDP_BASE + (off))
-
 #define MDP_HW_REV                              REG_MDP(0x1000)
 #define MDP_VP_0_VIG_0_BASE                     REG_MDP(0x5000)
+#define MDP_VP_0_VIG_1_BASE                     REG_MDP(0x7000)
 #define MDP_VP_0_RGB_0_BASE                     REG_MDP(0x15000)
+#define MDP_VP_0_RGB_1_BASE                     REG_MDP(0x17000)
 #define MDP_VP_0_DMA_0_BASE                     REG_MDP(0x25000)
+#define MDP_VP_0_DMA_1_BASE                     REG_MDP(0x27000)
 #define MDP_VP_0_MIXER_0_BASE                   REG_MDP(0x45000)
+#define MDP_VP_0_MIXER_1_BASE                   REG_MDP(0x46000)
 #define MDP_DISP_INTF_SEL                       REG_MDP(0x1004)
 #define MDP_VIDEO_INTF_UNDERFLOW_CTL            REG_MDP(0x12E0)
 #define MDP_UPPER_NEW_ROI_PRIOR_RO_START        REG_MDP(0x11EC)

diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
@@ -215,8 +215,8 @@
                                          (PERIPH_SS_BASE + 0x00163000 + \
                                          (qup_id * 0x1000)))
 
+/* MDSS */
 #define MSM_MMSS_CLK_CTL_BASE       0xFD8C0000
-
 #define MIPI_DSI_BASE               (0xFD922800)
 #define MIPI_DSI0_BASE              (MIPI_DSI_BASE)
 #define MIPI_DSI1_BASE              (0xFD922E00)
@@ -225,11 +225,17 @@
 #define DSI0_PLL_BASE               (0xFD922A00)
 #define DSI1_PLL_BASE               (0xFD923000)
 #define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
-
 #define EDP_BASE                    (0xFD923400)
-
 #define MDP_BASE                    (0xfd900000)
 #define REG_MDP(off)                (MDP_BASE + (off))
+#define MDP_VP_0_VIG_0_BASE          REG_MDP(0x1200)
+#define MDP_VP_0_VIG_1_BASE          REG_MDP(0x1600)
+#define MDP_VP_0_RGB_0_BASE          REG_MDP(0x1E00)
+#define MDP_VP_0_RGB_1_BASE          REG_MDP(0x2200)
+#define MDP_VP_0_DMA_0_BASE          REG_MDP(0x2A00)
+#define MDP_VP_0_DMA_1_BASE          REG_MDP(0x2E00)
+#define MDP_VP_0_MIXER_0_BASE        REG_MDP(0x3200)
+#define MDP_VP_0_MIXER_1_BASE        REG_MDP(0x3600)
 
 #define SOFT_RESET                  0x118
 #define CLK_CTRL                    0x11C

diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
@@ -32,13 +32,6 @@
 
 #include <msm_panel.h>
 
-#define MDP_VP_0_VIG_0_BASE                     REG_MDP(0x1200)
-#define MDP_VP_0_VIG_1_BASE                     REG_MDP(0x1600)
-#define MDP_VP_0_RGB_0_BASE                     REG_MDP(0x1E00)
-#define MDP_VP_0_RGB_1_BASE                     REG_MDP(0x2200)
-#define MDP_VP_0_DMA_0_BASE                     REG_MDP(0x2A00)
-#define MDP_VP_0_DMA_1_BASE                     REG_MDP(0x2E00)
-
 #define PIPE_SSPP_SRC0_ADDR                     0x14
 #define PIPE_SSPP_SRC_YSTRIDE                   0x24
 #define PIPE_SSPP_SRC_IMG_SIZE                  0x04
@@ -53,9 +46,6 @@
 #define REQPRIORITY_FIFO_WATERMARK1        	0x54
 #define REQPRIORITY_FIFO_WATERMARK2        	0x58
 
-#define MDP_VP_0_MIXER_0_BASE                   REG_MDP(0x3200)
-#define MDP_VP_0_MIXER_1_BASE                   REG_MDP(0x3600)
-
 #define LAYER_0_OUT_SIZE                        0x04
 #define LAYER_0_OP_MODE                         0x00
 #define LAYER_0_BORDER_COLOR_0                  0x08