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Run clang-format on PPC (capstone-engine#2157)
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@Rot127
Rot127 authored Sep 9, 2023
1 parent f3e7de8 commit 91fab10
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Showing 12 changed files with 496 additions and 432 deletions.
202 changes: 103 additions & 99 deletions arch/PowerPC/PPCDisassembler.c
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87 changes: 50 additions & 37 deletions arch/PowerPC/PPCInstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -50,18 +50,20 @@

// Static function declarations. These are functions which have the same identifiers
// over all architectures. Therefor they need to be static.
static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx,
unsigned PrintMethodIdx, SStream *O);
static void printCustomAliasOperand(MCInst *MI, uint64_t Address,
unsigned OpIdx, unsigned PrintMethodIdx,
SStream *O);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printPredicateOperand(MCInst *MI, unsigned OpNo, SStream *O,
const char *Modifier);
const char *Modifier);
static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O);
SStream *O);

#define PRINT_ALIAS_INSTR
#include "PPCGenAsmWriter.inc"

static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
bool isAlias = false;
bool useAliasDetails = false;
Expand All @@ -70,10 +72,9 @@ static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *
// operation, i.e:
// Transform: addis $rD, $rA, $src --> addis $rD, $src($rA).
if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs) &&
(MCInst_getOpcode(MI) == PPC_ADDIS8 ||
MCInst_getOpcode(MI) == PPC_ADDIS) &&
MCOperand_isExpr(MCInst_getOperand(MI, (2)))) {

(MCInst_getOpcode(MI) == PPC_ADDIS8 ||
MCInst_getOpcode(MI) == PPC_ADDIS) &&
MCOperand_isExpr(MCInst_getOperand(MI, (2)))) {
SStream_concat0(O, "\taddis ");
printOperand(MI, 0, O);
SStream_concat0(O, ", ");
Expand Down Expand Up @@ -111,7 +112,8 @@ static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *
SH = 32 - SH;
}
useAliasDetails |= map_use_alias_details(MI);
map_set_fill_detail_ops(MI, useAliasDetails && useSubstituteMnemonic);
map_set_fill_detail_ops(MI, useAliasDetails &&
useSubstituteMnemonic);
if (useSubstituteMnemonic) {
isAlias |= true;
MCInst_setIsAlias(MI, isAlias);
Expand All @@ -129,7 +131,7 @@ static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *
}

if (MCInst_getOpcode(MI) == PPC_RLDICR ||
MCInst_getOpcode(MI) == PPC_RLDICR_32) {
MCInst_getOpcode(MI) == PPC_RLDICR_32) {
unsigned char SH = MCOperand_getImm(MCInst_getOperand(MI, (2)));
unsigned char ME = MCOperand_getImm(MCInst_getOperand(MI, (3)));

Expand Down Expand Up @@ -163,8 +165,8 @@ static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *
// On AIX, only emit the extended mnemonics for dcbt and dcbtst if
// the "modern assembler" is available.
if ((MCInst_getOpcode(MI) == PPC_DCBT ||
MCInst_getOpcode(MI) == PPC_DCBTST) &&
(!PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs))) {
MCInst_getOpcode(MI) == PPC_DCBTST) &&
(!PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs))) {
unsigned char TH = MCOperand_getImm(MCInst_getOperand(MI, (0)));
SStream_concat0(O, "\tdcbt");
if (MCInst_getOpcode(MI) == PPC_DCBTST)
Expand All @@ -173,7 +175,8 @@ static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *
SStream_concat0(O, "t");
SStream_concat0(O, " ");

bool IsBookE = PPC_getFeatureBits(MI->csh->mode, PPC_FeatureBookE);
bool IsBookE =
PPC_getFeatureBits(MI->csh->mode, PPC_FeatureBookE);
if (IsBookE && TH != 0 && TH != 16) {
SStream_concat(O, "%s", (unsigned int)TH);
SStream_concat0(O, ", ");
Expand Down Expand Up @@ -235,7 +238,7 @@ static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *
}

void printPredicateOperand(MCInst *MI, unsigned OpNo, SStream *O,
const char *Modifier)
const char *Modifier)
{
add_cs_detail(MI, PPC_OP_GROUP_PredicateOperand, OpNo, Modifier);
unsigned Code = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
Expand Down Expand Up @@ -469,7 +472,8 @@ void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
add_cs_detail(MI, PPC_OP_GROUP_S16ImmOperand, OpNo);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNo))))
printInt32(O, (short)MCOperand_getImm(MCInst_getOperand(MI, (OpNo))));
printInt32(O, (short)MCOperand_getImm(
MCInst_getOperand(MI, (OpNo))));
else
printOperand(MI, OpNo, O);
}
Expand All @@ -478,7 +482,8 @@ void printS34ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
add_cs_detail(MI, PPC_OP_GROUP_S34ImmOperand, OpNo);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNo)))) {
long long Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
long long Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));

printInt64(O, (long long)Value);
} else
Expand All @@ -489,8 +494,8 @@ void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
add_cs_detail(MI, PPC_OP_GROUP_U16ImmOperand, OpNo);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNo))))
printUInt32(
O, (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, (OpNo))));
printUInt32(O, (unsigned short)MCOperand_getImm(
MCInst_getOperand(MI, (OpNo))));
else
printOperand(MI, OpNo, O);
}
Expand All @@ -501,7 +506,9 @@ void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O)
if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNo))))
return printOperand(MI, OpNo, O);
int32_t Imm = SignExtend32(
((unsigned)MCOperand_getImm(MCInst_getOperand(MI, (OpNo))) << 2), 32);
((unsigned)MCOperand_getImm(MCInst_getOperand(MI, (OpNo)))
<< 2),
32);
if (!MI->csh->PrintBranchImmNotAsAddress) {
uint64_t Target = Address + Imm;
if (!IS_64BIT(MI->csh->mode))
Expand All @@ -528,10 +535,10 @@ void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNo))))
return printOperand(MI, OpNo, O);

printInt32(
O, SignExtend32(
((unsigned)MCOperand_getImm(MCInst_getOperand(MI, (OpNo))) << 2),
32));
printInt32(O, SignExtend32(((unsigned)MCOperand_getImm(
MCInst_getOperand(MI, (OpNo)))
<< 2),
32));
}

void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O)
Expand Down Expand Up @@ -655,8 +662,9 @@ void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
/// printed with a percentage symbol as prefix.
bool showRegistersWithPercentPrefix(const MCInst *MI, const char *RegName)
{
if ((MI->csh->syntax & CS_OPT_SYNTAX_NOREGNAME) || !(MI->csh->syntax & CS_OPT_SYNTAX_PERCENT) ||
PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs))
if ((MI->csh->syntax & CS_OPT_SYNTAX_NOREGNAME) ||
!(MI->csh->syntax & CS_OPT_SYNTAX_PERCENT) ||
PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs))
return false;

switch (RegName[0]) {
Expand All @@ -674,19 +682,21 @@ bool showRegistersWithPercentPrefix(const MCInst *MI, const char *RegName)
/// getVerboseConditionalRegName - This method expands the condition register
/// when requested explicitly or targetting Darwin.
const char *getVerboseConditionRegName(const MCInst *MI, unsigned RegNum,
unsigned RegEncoding)
unsigned RegEncoding)
{
if (MI->csh->syntax & CS_OPT_SYNTAX_NOREGNAME)
return NULL;
if (RegNum < PPC_CR0EQ || RegNum > PPC_CR7UN)
return NULL;
const char *CRBits[] = {
"lt", "gt", "eq", "un", "4*cr1+lt", "4*cr1+gt",
"4*cr1+eq", "4*cr1+un", "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
"4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un", "4*cr4+lt", "4*cr4+gt",
"4*cr4+eq", "4*cr4+un", "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
"4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un", "4*cr7+lt", "4*cr7+gt",
"4*cr7+eq", "4*cr7+un"};
"lt", "gt", "eq", "un", "4*cr1+lt",
"4*cr1+gt", "4*cr1+eq", "4*cr1+un", "4*cr2+lt", "4*cr2+gt",
"4*cr2+eq", "4*cr2+un", "4*cr3+lt", "4*cr3+gt", "4*cr3+eq",
"4*cr3+un", "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
"4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un", "4*cr6+lt",
"4*cr6+gt", "4*cr6+eq", "4*cr6+un", "4*cr7+lt", "4*cr7+gt",
"4*cr7+eq", "4*cr7+un"
};
return CRBits[RegEncoding];
}

Expand All @@ -708,8 +718,8 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
&PPCInsts[MCInst_getOpcode(MI)], Reg, OpNo);

const char *RegName;
RegName =
getVerboseConditionRegName(MI, Reg, MI->MRI->RegEncodingTable[Reg]);
RegName = getVerboseConditionRegName(
MI, Reg, MI->MRI->RegEncodingTable[Reg]);
if (RegName == NULL)
RegName = getRegisterName(Reg);
if (showRegistersWithPercentPrefix(MI, RegName))
Expand All @@ -727,10 +737,13 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
}
}

const char *PPC_LLVM_getRegisterName(unsigned RegNo) {
const char *PPC_LLVM_getRegisterName(unsigned RegNo)
{
return getRegisterName(RegNo);
}

void PPC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O) {
void PPC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
printInst(MI, Address, Annot, O);
}
2 changes: 1 addition & 1 deletion arch/PowerPC/PPCInstPrinter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ void printS34ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printImmZeroOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
SStream *O);
SStream *O);
void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O);
void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O);
Expand Down
55 changes: 29 additions & 26 deletions arch/PowerPC/PPCInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,13 @@

extern const MCInstrDesc PPCInsts[];

static bool isVFRegister(unsigned Reg) {
return Reg >= PPC_VF0 && Reg <= PPC_VF31;
static bool isVFRegister(unsigned Reg)
{
return Reg >= PPC_VF0 && Reg <= PPC_VF31;
}
static bool isVRRegister(unsigned Reg) {
return Reg >= PPC_V0 && Reg <= PPC_V31;
static bool isVRRegister(unsigned Reg)
{
return Reg >= PPC_V0 && Reg <= PPC_V31;
}

/// getRegNumForOperand - some operands use different numbering schemes
Expand All @@ -23,28 +25,29 @@ static bool isVRRegister(unsigned Reg) {
/// The operand number argument will be useful when we need to extend this
/// to instructions that use both Altivec and VSX numbering (for different
/// operands).
static unsigned PPCInstrInfo_getRegNumForOperand(const MCInstrDesc *Desc, unsigned Reg,
unsigned OpNo) {
int16_t regClass = Desc->OpInfo[OpNo].RegClass;
switch (regClass) {
// We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
// VSX32-VSX63 during encoding/disassembling
case PPC_VSSRCRegClassID:
case PPC_VSFRCRegClassID:
if (isVFRegister(Reg))
return PPC_VSX32 + (Reg - PPC_VF0);
break;
// We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
// VSX32-VSX63 during encoding/disassembling
case PPC_VSRCRegClassID:
if (isVRRegister(Reg))
return PPC_VSX32 + (Reg - PPC_V0);
break;
// Other RegClass doesn't need mapping
default:
break;
}
return Reg;
static unsigned PPCInstrInfo_getRegNumForOperand(const MCInstrDesc *Desc,
unsigned Reg, unsigned OpNo)
{
int16_t regClass = Desc->OpInfo[OpNo].RegClass;
switch (regClass) {
// We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
// VSX32-VSX63 during encoding/disassembling
case PPC_VSSRCRegClassID:
case PPC_VSFRCRegClassID:
if (isVFRegister(Reg))
return PPC_VSX32 + (Reg - PPC_VF0);
break;
// We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
// VSX32-VSX63 during encoding/disassembling
case PPC_VSRCRegClassID:
if (isVRRegister(Reg))
return PPC_VSX32 + (Reg - PPC_V0);
break;
// Other RegClass doesn't need mapping
default:
break;
}
return Reg;
}

#endif // CS_PPC_INSTRINFO_H
9 changes: 5 additions & 4 deletions arch/PowerPC/PPCLinkage.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,11 @@
#include "../../SStream.h"
#include "capstone/capstone.h"

DecodeStatus PPC_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
MCInst *MI, uint16_t *Size, uint64_t Address,
void *Info);
DecodeStatus PPC_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI, uint16_t *Size,
uint64_t Address, void *Info);
const char *PPC_LLVM_getRegisterName(unsigned RegNo);
void PPC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
void PPC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O);

#endif // CS_PPC_LINKAGE_H
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