Support RegisterPreset annotations

Evaluation support is a bit primitive. When registers with async reset types are matched with a RegisterPresetAnnoation then the raw datastore is initialized with the literal reset value.
chipsalliance · May 28, 2021 · 371c846 · 371c846
1 parent 9a32b39
commit 371c846
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Showing 5 changed files with 568 additions and 321 deletions.
diff --git a/src/main/scala/treadle/executable/ExecutionEngine.scala b/src/main/scala/treadle/executable/ExecutionEngine.scala
@@ -3,8 +3,7 @@
 package treadle.executable
 
 import java.io.{File, PrintWriter}
-
-import firrtl.annotations.ReferenceTarget
+import firrtl.annotations.{PresetAnnotation, ReferenceTarget}
 import firrtl.annotations.TargetToken.Instance
 import firrtl.ir.{Circuit, NoInfo}
 import firrtl.options.StageOptions
@@ -606,6 +605,7 @@ object ExecutionEngine extends LazyLogging {
       .map { s =>
         PlusArg(s)
       }
+    val registerPresets: Seq[ReferenceTarget] = annotationSeq.collect { case PresetAnnotation(target) => target }
 
     val validIfIsRandom = annotationSeq.exists { case ValidIfIsRandomAnnotation => true; case _ => false }
     val verbose = annotationSeq.exists { case VerboseAnnotation => true; case _ => false }
@@ -633,11 +633,12 @@ object ExecutionEngine extends LazyLogging {
       validIfIsRandom,
       prefixPrintfWithTime,
       blackBoxFactories,
-      plusArgs
+      plusArgs,
+      registerPresets
     )
 
     timer("Build Compiled Expressions") {
-      compiler.compile(circuit, blackBoxFactories)
+      compiler.compile(circuit)
     }
 
     val expressionViews: Map[Symbol, ExpressionView] = ExpressionViewBuilder.getExpressionViews(

diff --git a/src/main/scala/treadle/executable/ExpressionCompiler.scala b/src/main/scala/treadle/executable/ExpressionCompiler.scala
@@ -4,6 +4,7 @@ package treadle.executable
 
 import firrtl.PrimOps._
 import firrtl._
+import firrtl.annotations.ReferenceTarget
 import firrtl.ir._
 import treadle._
 import treadle.blackboxes.PlusArg
@@ -18,7 +19,8 @@ class ExpressionCompiler(
   validIfIsRandom:      Boolean,
   prefixPrintfWithTime: Boolean,
   blackBoxFactories:    Seq[ScalaBlackBoxFactory],
-  plusArgs:             Seq[PlusArg])
+  plusArgs:             Seq[PlusArg],
+  presetTargets:        Seq[ReferenceTarget])
     extends logger.LazyLogging {
 
   case class ExternalInputParams(instance: ScalaBlackBox, portName: String)
@@ -32,6 +34,19 @@ class ExpressionCompiler(
     }
   }
 
+  // Preset registers have references to the async reset
+  private val presetTargetList = presetTargets.map { presetTarget =>
+    val pathSteps = mutable.ArrayBuffer[String]()
+    var element = presetTarget.path
+    while (element.nonEmpty) {
+      val step = element.head._1.value
+      pathSteps += step
+      element = element.tail
+    }
+    pathSteps += presetTarget.ref
+    pathSteps.mkString(".")
+  }
+
   def getWidth(expression: Expression): Int = {
     expression.tpe match {
       case GroundType(IntWidth(width)) => width.toInt
@@ -206,6 +221,7 @@ class ExpressionCompiler(
   //scalastyle:off method.length
   def processStatements(modulePrefix: String, circuit: Circuit, statement: firrtl.ir.Statement): Unit = {
     def expand(name: String): String = if (modulePrefix.isEmpty) name else modulePrefix + "." + name
+    def moduleName: String = modulePrefix.split(".").lastOption.getOrElse("")
 
     @scala.annotation.tailrec
     def getDrivingClock(clockExpression: Expression): Option[Symbol] = {
@@ -872,6 +888,23 @@ class ExpressionCompiler(
               val asyncResetMux = processMux(asyncResetCondition, processExpression(initExpression), posEdgeMux)
 
               makeAssigner(registerOut, asyncResetMux, info = info)
+
+              resetExpression match {
+                case Reference(resetName, _, _, _) =>
+                  val fullResetName = expand(resetName)
+                  if (presetTargetList.contains(fullResetName)) {
+                    val initValue = processExpression(initExpression) match {
+                      case GetIntConstant(value)  => BigInt(value)
+                      case GetLongConstant(value) => BigInt(value)
+                      case GetBigConstant(value)  => value
+                      case badValue =>
+                        throw TreadleException(s"Error:RegisterPresetValue should be literal got: $badValue")
+                    }
+                    dataStore.update(registerOut, initValue)
+                    dataStore.update(registerIn, initValue)
+                  }
+                case _ =>
+              }
             } else {
               //TODO: (Chick) We could use
               // makeAssigner(registerOut, posEdgeMux, info = info)
@@ -1024,7 +1057,7 @@ class ExpressionCompiler(
   }
 
   // scalastyle:off cyclomatic.complexity
-  def compile(circuit: Circuit, blackBoxFactories: Seq[ScalaBlackBoxFactory]): Unit = {
+  def compile(circuit: Circuit): Unit = {
     val module = FindModule(circuit.main, circuit) match {
       case regularModule:  firrtl.ir.Module => regularModule
       case externalModule: firrtl.ir.ExtModule =>

diff --git a/src/main/scala/treadle/executable/Symbol.scala b/src/main/scala/treadle/executable/Symbol.scala
@@ -2,6 +2,7 @@
 
 package treadle.executable
 
+import firrtl.annotations.ReferenceTarget
 import firrtl.ir.{Info, IntWidth, NoInfo}
 import firrtl.{Kind, WireKind}
 import treadle._
@@ -81,6 +82,11 @@ case class Symbol(
     f"$name%-40.40s $dataSize%3.3s $dataType%4.4s $bitWidth%6d " +
       f"$slots%6d $index%6d$dataSizeCode $cardinalNumber%6d $info"
   }
+
+  def matches(referenceTarget: ReferenceTarget): Boolean = {
+    val refString = referenceTarget.ref
+    true
+  }
 }
 
 object Symbol {

diff --git a/src/main/scala/treadle/executable/SymbolTable.scala b/src/main/scala/treadle/executable/SymbolTable.scala
@@ -3,6 +3,7 @@
 package treadle.executable
 
 import firrtl._
+import firrtl.annotations.ReferenceTarget
 import firrtl.graph.DiGraph
 import firrtl.ir._
 import logger.LazyLogging