Removed verbose mode, and vcd output from test (#368)

Cleaned up imports
chipsalliance · Sep 29, 2021 · d0baa44 · d0baa44
1 parent 279338b
commit d0baa44
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Showing 2 changed files with 1 addition and 3 deletions.
diff --git a/src/main/scala/treadle/executable/SymbolTable.scala b/src/main/scala/treadle/executable/SymbolTable.scala
@@ -3,7 +3,6 @@
 package treadle.executable
 
 import firrtl._
-import firrtl.annotations.ReferenceTarget
 import firrtl.graph.DiGraph
 import firrtl.ir._
 import logger.LazyLogging

diff --git a/src/test/scala/treadle/StopBehaviorSpec.scala b/src/test/scala/treadle/StopBehaviorSpec.scala
@@ -6,7 +6,6 @@ import firrtl.ir.NoInfo
 
 import java.io.{ByteArrayOutputStream, PrintStream}
 import firrtl.stage.FirrtlSourceAnnotation
-import logger.{LogLevel, LogLevelAnnotation}
 import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 import treadle.executable.StopException
@@ -263,7 +262,7 @@ class StopBehaviorSpec extends AnyFreeSpec with Matchers {
         |    c0.stop0En <= and(selChild0, stop0En)
         |""".stripMargin
 
-    TreadleTestHarness(Seq(FirrtlSourceAnnotation(input), VerboseAnnotation, WriteVcdAnnotation)) { tester =>
+    TreadleTestHarness(Seq(FirrtlSourceAnnotation(input))) { tester =>
       // set every input to zero by default
       tester.poke("stop0En", 0)
       tester.poke("selParent", 0)