all: Update reserved function names

Update reserved function names starting with one underscore, replacing
them as follows:
   '_k_' with 'z_'
   '_K_' with 'Z_'
   '_handler_' with 'z_handl_'
   '_Cstart' with 'z_cstart'
   '_Swap' with 'z_swap'

This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.

Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.

Various generator scripts have also been updated as well as perf,
linker and usb files. These are
   drivers/serial/uart_handlers.c
   include/linker/kobject-text.ld
   kernel/include/syscall_handler.h
   scripts/gen_kobject_list.py
   scripts/gen_syscall_header.py

Signed-off-by: Patrik Flykt <[email protected]>

arch/arc/core/cache.c

@@ -51,7 +51,7 @@
 
 static bool dcache_available(void)
 {
-	unsigned long val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	unsigned long val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
 
 	val &= 0xff; /* extract version */
 	return (val == 0) ? false : true;
@@ -60,7 +60,7 @@ static bool dcache_available(void)
 static void dcache_dc_ctrl(u32_t dcache_en_mask)
 {
 	if (dcache_available()) {
-		_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, dcache_en_mask);
+		z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, dcache_en_mask);
 	}
 }
 
@@ -101,13 +101,13 @@ static void dcache_flush_mlines(u32_t start_addr, u32_t size)
 	key = irq_lock(); /* --enter critical section-- */
 
 	do {
-		_arc_v2_aux_reg_write(_ARC_V2_DC_FLDL, start_addr);
+		z_arc_v2_aux_reg_write(_ARC_V2_DC_FLDL, start_addr);
 		__asm__ volatile("nop_s");
 		__asm__ volatile("nop_s");
 		__asm__ volatile("nop_s");
 		/* wait for flush completion */
 		do {
-			if ((_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) &
+			if ((z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) &
 			     DC_CTRL_FLUSH_STATUS) == 0) {
 				break;
 			}
@@ -149,7 +149,7 @@ static void init_dcache_line_size(void)
 {
 	u32_t val;
 
-	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
 	__ASSERT((val&0xff) != 0, "d-cache is not present");
 	val = ((val>>16) & 0xf) + 1;
 	val *= 16;

arch/arc/core/fast_irq.S

@@ -145,7 +145,7 @@ SECTION_FUNC(TEXT, _firq_exit)
 	st	r0, [r1]
 
 #ifdef CONFIG_STACK_SENTINEL
-	bl _check_stack_sentinel
+	bl z_check_stack_sentinel
 #endif
 
 #ifdef CONFIG_PREEMPT_ENABLED
@@ -284,7 +284,7 @@ _firq_return_from_coop:
 	pop_s r0 /* status32 into r0 */
 	/*
 	 * There are only two interrupt lock states: locked and unlocked. When
-	 * entering _Swap(), they are always locked, so the IE bit is unset in
+	 * entering z_swap(), they are always locked, so the IE bit is unset in
 	 * status32. If the incoming thread had them locked recursively, it
 	 * means that the IE bit should stay unset. The only time the bit
 	 * has to change is if they were not locked recursively.

arch/arc/core/fatal.c

@@ -25,7 +25,7 @@
  *
  * This routine is called when fatal error conditions are detected by software
  * and is responsible only for reporting the error. Once reported, it then
- * invokes the user provided routine _SysFatalErrorHandler() which is
+ * invokes the user provided routine z_SysFatalErrorHandler() which is
  * responsible for implementing the error handling policy.
  *
  * The caller is expected to always provide a usable ESF. In the event that the
@@ -34,7 +34,7 @@
  *
  * @return This function does not return.
  */
-void _NanoFatalErrorHandler(unsigned int reason, const NANO_ESF *pEsf)
+void z_NanoFatalErrorHandler(unsigned int reason, const NANO_ESF *pEsf)
 {
 	LOG_PANIC();
 
@@ -70,7 +70,7 @@ void _NanoFatalErrorHandler(unsigned int reason, const NANO_ESF *pEsf)
 
 	if (reason == _NANO_ERR_HW_EXCEPTION) {
 		printk("Faulting instruction address = 0x%lx\n",
-		_arc_v2_aux_reg_read(_ARC_V2_ERET));
+		z_arc_v2_aux_reg_read(_ARC_V2_ERET));
 	}
 
 	/*
@@ -81,12 +81,12 @@ void _NanoFatalErrorHandler(unsigned int reason, const NANO_ESF *pEsf)
 	 * decide.
 	 */
 
-	_SysFatalErrorHandler(reason, pEsf);
+	z_SysFatalErrorHandler(reason, pEsf);
 }
 
-FUNC_NORETURN void _arch_syscall_oops(void *ssf_ptr)
+FUNC_NORETURN void z_arch_syscall_oops(void *ssf_ptr)
 {
 	LOG_PANIC();
-	_SysFatalErrorHandler(_NANO_ERR_KERNEL_OOPS, ssf_ptr);
+	z_SysFatalErrorHandler(_NANO_ERR_KERNEL_OOPS, ssf_ptr);
 	CODE_UNREACHABLE;
 }

arch/arc/core/fault.c

@@ -34,14 +34,14 @@ static const struct z_exc_handle exceptions[] = {
  *
  * This routine is called when fatal error conditions are detected by hardware
  * and is responsible only for reporting the error. Once reported, it then
- * invokes the user provided routine _SysFatalErrorHandler() which is
+ * invokes the user provided routine z_SysFatalErrorHandler() which is
  * responsible for implementing the error handling policy.
  */
 void _Fault(NANO_ESF *esf)
 {
 	u32_t vector, code, parameter;
-	u32_t exc_addr = _arc_v2_aux_reg_read(_ARC_V2_EFA);
-	u32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
+	u32_t exc_addr = z_arc_v2_aux_reg_read(_ARC_V2_EFA);
+	u32_t ecr = z_arc_v2_aux_reg_read(_ARC_V2_ECR);
 
 	LOG_PANIC();
 
@@ -64,7 +64,7 @@ void _Fault(NANO_ESF *esf)
 
 	/* exception raised by kernel */
 	if (vector == 0x9 && parameter == _TRAP_S_CALL_RUNTIME_EXCEPT) {
-		_NanoFatalErrorHandler(esf->r0, esf);
+		z_NanoFatalErrorHandler(esf->r0, esf);
 		return;
 	}
 
@@ -76,9 +76,9 @@ void _Fault(NANO_ESF *esf)
 	 * check violation
 	 */
 	if (vector == 6 && parameter == 2) {
-		_NanoFatalErrorHandler(_NANO_ERR_STACK_CHK_FAIL, esf);
+		z_NanoFatalErrorHandler(_NANO_ERR_STACK_CHK_FAIL, esf);
 		return;
 	}
 #endif
-	_NanoFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, esf);
+	z_NanoFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, esf);
 }

arch/arc/core/irq_manage.c

@@ -36,7 +36,7 @@
  * @return N/A
  */
 
-void _arch_irq_enable(unsigned int irq)
+void z_arch_irq_enable(unsigned int irq)
 {
 	unsigned int key = irq_lock();
 
@@ -53,7 +53,7 @@ void _arch_irq_enable(unsigned int irq)
  * @return N/A
  */
 
-void _arch_irq_disable(unsigned int irq)
+void z_arch_irq_disable(unsigned int irq)
 {
 	unsigned int key = irq_lock();
 
@@ -75,7 +75,7 @@ void _arch_irq_disable(unsigned int irq)
  * @return N/A
  */
 
-void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
+void z_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
 {
 	ARG_UNUSED(flags);
 
@@ -96,22 +96,22 @@ void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
  * @return N/A
  */
 
-void _irq_spurious(void *unused)
+void z_irq_spurious(void *unused)
 {
 	ARG_UNUSED(unused);
-	printk("_irq_spurious(). Spinning...\n");
+	printk("z_irq_spurious(). Spinning...\n");
 	for (;;) {
 		;
 	}
 }
 
 #ifdef CONFIG_DYNAMIC_INTERRUPTS
-int _arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
+int z_arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
 			      void (*routine)(void *parameter), void *parameter,
 			      u32_t flags)
 {
 	z_isr_install(irq, routine, parameter);
-	_irq_priority_set(irq, priority, flags);
+	z_irq_priority_set(irq, priority, flags);
 	return irq;
 }
 #endif /* CONFIG_DYNAMIC_INTERRUPTS */

arch/arc/core/isr_wrapper.S

@@ -45,7 +45,7 @@ SECTION_VAR(BSS, saved_sp)
 #endif
 
 #if defined(CONFIG_SYS_POWER_MANAGEMENT)
-GTEXT(_sys_power_save_idle_exit)
+GTEXT(z_sys_power_save_idle_exit)
 #endif
 
 /*
@@ -95,7 +95,7 @@ The context switch code adopts this standard so that it is easier to follow:
     transition from outgoing thread to incoming thread
 
 Not loading _kernel into r0 allows loading _kernel without stomping on
-the parameter in r0 in _Swap().
+the parameter in r0 in z_swap().
 
 
 ARCv2 processors have two kinds of interrupts: fast (FIRQ) and regular. The
@@ -195,7 +195,7 @@ From FIRQ:
 
   o to coop
 
-    The address of the returning instruction from _Swap() is loaded in ilink and
+    The address of the returning instruction from z_swap() is loaded in ilink and
     the saved status32 in status32_p0, taking care to adjust the interrupt lock
     state desired in status32_p0. The return value is put in r0.
 
@@ -359,7 +359,7 @@ GTEXT(z_sys_trace_isr_enter)
 
 	st 0, [r1, _kernel_offset_to_idle] /* zero idle duration */
 	push_s blink
-	jl _sys_power_save_idle_exit
+	jl z_sys_power_save_idle_exit
 	pop_s blink
 
 _skip_sys_power_save_idle_exit:

arch/arc/core/mpu/arc_core_mpu.c

@@ -104,15 +104,15 @@ void configure_mpu_mem_domain(struct k_thread *thread)
 	arc_core_mpu_configure_mem_domain(thread);
 }
 
-int _arch_mem_domain_max_partitions_get(void)
+int z_arch_mem_domain_max_partitions_get(void)
 {
 	return arc_core_mpu_get_max_domain_partition_regions();
 }
 
 /*
  * Reset MPU region for a single memory partition
  */
-void _arch_mem_domain_partition_remove(struct k_mem_domain *domain,
+void z_arch_mem_domain_partition_remove(struct k_mem_domain *domain,
 				       u32_t partition_id)
 {
 	ARG_UNUSED(domain);
@@ -126,15 +126,15 @@ void _arch_mem_domain_partition_remove(struct k_mem_domain *domain,
 /*
  * Configure MPU memory domain
  */
-void _arch_mem_domain_configure(struct k_thread *thread)
+void z_arch_mem_domain_configure(struct k_thread *thread)
 {
 	configure_mpu_mem_domain(thread);
 }
 
 /*
  * Destroy MPU regions for the mem domain
  */
-void _arch_mem_domain_destroy(struct k_mem_domain *domain)
+void z_arch_mem_domain_destroy(struct k_mem_domain *domain)
 {
 	ARG_UNUSED(domain);
 
@@ -152,7 +152,7 @@ void _arch_mem_domain_partition_add(struct k_mem_domain *domain,
 /*
  * Validate the given buffer is user accessible or not
  */
-int _arch_buffer_validate(void *addr, size_t size, int write)
+int z_arch_buffer_validate(void *addr, size_t size, int write)
 {
 	return arc_core_mpu_buffer_validate(addr, size, write);
 }