can: flexcan: fix irq flooding by clearing all interrupt sources

As pointed out by Reuben Dowle and Lothar Waßmann, the TWRN_INT, RWRN_INT, BOFF_INT interrupt sources need to be cleared as well to avoid interrupt flooding, at least for the Flexcan on i.MX28 SOCs. Furthermore, the interrupts are only cleared, if really one of those interrupt sources are pending (which is not the case for rx and tx done). Cc: Reuben Dowle <[email protected]> Cc: Lothar Waßmann <[email protected]> Signed-off-by: Wolfgang Grandegger <[email protected]> Signed-off-by: Marc Kleine-Budde <[email protected]>
cluon · Feb 2, 2012 · 6e9d554 · 6e9d554
1 parent ba76057
commit 6e9d554
Showing 1 changed file with 6 additions and 1 deletion.
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
@@ -118,6 +118,9 @@
 	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 #define FLEXCAN_ESR_ERR_ALL \
 	(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
+#define FLEXCAN_ESR_ALL_INT \
+	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
+	 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 
 /* FLEXCAN interrupt flag register (IFLAG) bits */
 #define FLEXCAN_TX_BUF_ID		8
@@ -577,7 +580,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 
 	reg_iflag1 = flexcan_read(&regs->iflag1);
 	reg_esr = flexcan_read(&regs->esr);
-	flexcan_write(FLEXCAN_ESR_ERR_INT, &regs->esr);	/* ACK err IRQ */
+	/* ACK all bus error and state change IRQ sources */
+	if (reg_esr & FLEXCAN_ESR_ALL_INT)
+		flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 
 	/*
 	 * schedule NAPI in case of: