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@GhidorahRex
GhidorahRex committed Mar 4, 2020
2 parents f4ce863 + b06ca0c commit ddc6377
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4 changes: 2 additions & 2 deletions Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
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Expand Up @@ -1837,8 +1837,8 @@ is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1
# C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 KEEPWITH
# sf == 0 && sz = 00 CRC32CB variant

crcpoly: "" is b_12=0 { local tmp = 0x04C11DB7:4; export *[const]:4 tmp; }
crcpoly: "c" is b_12=1 { local tmp = 0x1EDC6F41:4; export *[const]:4 tmp; }
crcpoly: "" is b_12=0 {export *[const]:4 0x04C11DB7:4; }
crcpoly: "c" is b_12=1 { export *[const]:4 0x1EDC6F41:4; }

# C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 MATCH x1ac04000/mask=x7fe0f000
# C6.2.60 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-613 line 35898 MATCH x1ac05000/mask=x7fe0f000
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10 changes: 5 additions & 5 deletions Ghidra/Processors/Atmel/data/languages/avr32a.slaspec
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Expand Up @@ -637,19 +637,19 @@ RBSelector: rb9[ri0"<U> << 2]" is rb9 & ri0; selectorxy4_2=0x2 { ptr:4 = rb9 + (
RBSelector: rb9[ri0"<T> << 2]" is rb9 & ri0; selectorxy4_2=0x3 { ptr:4 = rb9 + (((ri0 >> 24) & 0xff) << 0x02); export ptr; }

RS0A: rs0 is rs0 { export rs0; }
RS0A: rs0 is rs0 & rs0=0xf { tmp:4 = inst_start; export *[const]:4 tmp; }
RS0A: rs0 is rs0 & rs0=0xf { export inst_start; }

RS9A: rs9 is rs9 { export rs9; }
RS9A: rs9 is rs9 & rs9=0xf { tmp:4 = inst_start; export *[const]:4 tmp; }
RS9A: rs9 is rs9 & rs9=0xf { export inst_start; }

RX9A: rx9 is rx9 { export rx9; }
RX9A: rx9 is rx9 & rx9=0xf { tmp:4 = inst_start; export *[const]:4 tmp; }
RX9A: rx9 is rx9 & rx9=0xf { export inst_start; }

RY0A: ry0 is ry0 { export ry0; }
RY0A: ry0 is ry0 & ry0=0xf { tmp:4 = inst_start; export *[const]:4 tmp; }
RY0A: ry0 is ry0 & ry0=0xf { export inst_start; }

RD0A: rd0 is rd0 { export rd0; }
RD0A: rd0 is rd0 & rd0=0xf { tmp:4 = inst_start; export *[const]:4 tmp; }
RD0A: rd0 is rd0 & rd0=0xf { export inst_start; }

macro ZSTATUS(RES) {
Z = RES == 0;
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72 changes: 36 additions & 36 deletions Ghidra/Processors/Atmel/data/languages/avr32a_dsp_operations2.sinc
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Expand Up @@ -29,31 +29,31 @@ XPART: ":T" is ctx_usex & xpart=0x1 {
tmp = tmp >> 16;
tmpa:2 = tmp:2;
tmpb:4 = sext(tmpa);
export *[const]:4 tmpb;
export *:4 tmpb;
}

XPART: ":B" is ctx_usex & xpart=0x0 {
tmp:4 = ctx_usex;
tmp = tmp & 0xFFFF;
tmpa:2 = tmp:2;
tmpb:4 = sext(tmpa);
export *[const]:4 tmpb;
export *:4 tmpb;
}

YPART: ":T" is ctx_usey & ypart=0x1 {
tmp:4 = ctx_usey;
tmp = tmp >> 16;
tmpa:2 = tmp:2;
tmpb:4 = sext(tmpa);
export *[const]:4 tmpb;
export *:4 tmpb;
}

YPART: ":B" is ctx_usey & ypart=0x0 {
tmp:4 = ctx_usey;
tmp = tmp & 0xFFFF;
tmpa:2 = tmp:2;
tmpb:4 = sext(tmpa);
export *[const]:4 tmpb;
export *:4 tmpb;
}

:ADDHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ;
Expand Down Expand Up @@ -248,38 +248,38 @@ YPART: ":B" is ctx_usey & ypart=0x0 {



SATM: is ebp5_5=0 { tmp:4 = 0x00000000; export *[const]:4 tmp; }
SATM: is ebp5_5=1 { tmp:4 = 0xFFFFFFFF; export *[const]:4 tmp; }
SATM: is ebp5_5=2 { tmp:4 = 0xFFFFFFFE; export *[const]:4 tmp; }
SATM: is ebp5_5=3 { tmp:4 = 0xFFFFFFFC; export *[const]:4 tmp; }
SATM: is ebp5_5=4 { tmp:4 = 0xFFFFFFF8; export *[const]:4 tmp; }
SATM: is ebp5_5=5 { tmp:4 = 0xFFFFFFF0; export *[const]:4 tmp; }
SATM: is ebp5_5=6 { tmp:4 = 0xFFFFFFE0; export *[const]:4 tmp; }
SATM: is ebp5_5=7 { tmp:4 = 0xFFFFFFC0; export *[const]:4 tmp; }
SATM: is ebp5_5=8 { tmp:4 = 0xFFFFFF80; export *[const]:4 tmp; }
SATM: is ebp5_5=9 { tmp:4 = 0xFFFFFF00; export *[const]:4 tmp; }
SATM: is ebp5_5=10 { tmp:4 = 0xFFFFFE00; export *[const]:4 tmp; }
SATM: is ebp5_5=11 { tmp:4 = 0xFFFFFC00; export *[const]:4 tmp; }
SATM: is ebp5_5=12 { tmp:4 = 0xFFFFF800; export *[const]:4 tmp; }
SATM: is ebp5_5=13 { tmp:4 = 0xFFFFF000; export *[const]:4 tmp; }
SATM: is ebp5_5=14 { tmp:4 = 0xFFFFE000; export *[const]:4 tmp; }
SATM: is ebp5_5=15 { tmp:4 = 0xFFFFC000; export *[const]:4 tmp; }
SATM: is ebp5_5=16 { tmp:4 = 0xFFFF8000; export *[const]:4 tmp; }
SATM: is ebp5_5=17 { tmp:4 = 0xFFFF0000; export *[const]:4 tmp; }
SATM: is ebp5_5=18 { tmp:4 = 0xFFFE0000; export *[const]:4 tmp; }
SATM: is ebp5_5=19 { tmp:4 = 0xFFFC0000; export *[const]:4 tmp; }
SATM: is ebp5_5=20 { tmp:4 = 0xFFF80000; export *[const]:4 tmp; }
SATM: is ebp5_5=21 { tmp:4 = 0xFFF00000; export *[const]:4 tmp; }
SATM: is ebp5_5=22 { tmp:4 = 0xFFE00000; export *[const]:4 tmp; }
SATM: is ebp5_5=23 { tmp:4 = 0xFFC00000; export *[const]:4 tmp; }
SATM: is ebp5_5=24 { tmp:4 = 0xFF800000; export *[const]:4 tmp; }
SATM: is ebp5_5=25 { tmp:4 = 0xFF000000; export *[const]:4 tmp; }
SATM: is ebp5_5=26 { tmp:4 = 0xFE000000; export *[const]:4 tmp; }
SATM: is ebp5_5=27 { tmp:4 = 0xFC000000; export *[const]:4 tmp; }
SATM: is ebp5_5=28 { tmp:4 = 0xF8000000; export *[const]:4 tmp; }
SATM: is ebp5_5=29 { tmp:4 = 0xF0000000; export *[const]:4 tmp; }
SATM: is ebp5_5=30 { tmp:4 = 0xE0000000; export *[const]:4 tmp; }
SATM: is ebp5_5=31 { tmp:4 = 0xC0000000; export *[const]:4 tmp; }
SATM: is ebp5_5=0 { tmp:4 = 0x00000000; export tmp; }
SATM: is ebp5_5=1 { tmp:4 = 0xFFFFFFFF; export tmp; }
SATM: is ebp5_5=2 { tmp:4 = 0xFFFFFFFE; export tmp; }
SATM: is ebp5_5=3 { tmp:4 = 0xFFFFFFFC; export tmp; }
SATM: is ebp5_5=4 { tmp:4 = 0xFFFFFFF8; export tmp; }
SATM: is ebp5_5=5 { tmp:4 = 0xFFFFFFF0; export tmp; }
SATM: is ebp5_5=6 { tmp:4 = 0xFFFFFFE0; export tmp; }
SATM: is ebp5_5=7 { tmp:4 = 0xFFFFFFC0; export tmp; }
SATM: is ebp5_5=8 { tmp:4 = 0xFFFFFF80; export tmp; }
SATM: is ebp5_5=9 { tmp:4 = 0xFFFFFF00; export tmp; }
SATM: is ebp5_5=10 { tmp:4 = 0xFFFFFE00; export tmp; }
SATM: is ebp5_5=11 { tmp:4 = 0xFFFFFC00; export tmp; }
SATM: is ebp5_5=12 { tmp:4 = 0xFFFFF800; export tmp; }
SATM: is ebp5_5=13 { tmp:4 = 0xFFFFF000; export tmp; }
SATM: is ebp5_5=14 { tmp:4 = 0xFFFFE000; export tmp; }
SATM: is ebp5_5=15 { tmp:4 = 0xFFFFC000; export tmp; }
SATM: is ebp5_5=16 { tmp:4 = 0xFFFF8000; export tmp; }
SATM: is ebp5_5=17 { tmp:4 = 0xFFFF0000; export tmp; }
SATM: is ebp5_5=18 { tmp:4 = 0xFFFE0000; export tmp; }
SATM: is ebp5_5=19 { tmp:4 = 0xFFFC0000; export tmp; }
SATM: is ebp5_5=20 { tmp:4 = 0xFFF80000; export tmp; }
SATM: is ebp5_5=21 { tmp:4 = 0xFFF00000; export tmp; }
SATM: is ebp5_5=22 { tmp:4 = 0xFFE00000; export tmp; }
SATM: is ebp5_5=23 { tmp:4 = 0xFFC00000; export tmp; }
SATM: is ebp5_5=24 { tmp:4 = 0xFF800000; export tmp; }
SATM: is ebp5_5=25 { tmp:4 = 0xFF000000; export tmp; }
SATM: is ebp5_5=26 { tmp:4 = 0xFE000000; export tmp; }
SATM: is ebp5_5=27 { tmp:4 = 0xFC000000; export tmp; }
SATM: is ebp5_5=28 { tmp:4 = 0xF8000000; export tmp; }
SATM: is ebp5_5=29 { tmp:4 = 0xF0000000; export tmp; }
SATM: is ebp5_5=30 { tmp:4 = 0xE0000000; export tmp; }
SATM: is ebp5_5=31 { tmp:4 = 0xC0000000; export tmp; }

:SATRNDS rd0^" >> "^esa0_5, ebp5_5^SATM is op4_12=0xf3b & rd0 ;
eop10_6=0x0 & esa0_5 & ebp5_5 & SATM
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8 changes: 4 additions & 4 deletions Ghidra/Processors/MIPS/data/languages/mips16.sinc
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Expand Up @@ -137,11 +137,11 @@ EXT_IS0: val is m16_i_imm [ val = m16_i_imm << 0; ] { export *[const]:2 val
EXT_IS1: val is m16_i_imm [ val = m16_i_imm << 1; ] { export *[const]:2 val; }
EXT_RI: val is ext_value_1511 & ext_value_1005 & m16_ri_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_ri_imm; ] { export *[const]:2 val; }
EXT_RRIA: val is ext_is_ext=1 & ext_value_1411s & ext_value_1004 & m16_rria_imm [ val=(ext_value_1411s << 11) | (ext_value_1004 << 4) | m16_rria_imm; ] { export *[const]:2 val; }
EXT_RRIA: m16_rria_simm is ext_is_ext=0 & m16_rria_simm { tmp:1 = m16_rria_simm; tmpa:2 = sext(tmp); export *[const]:2 tmpa; }
EXT_RRIA: m16_rria_simm is ext_is_ext=0 & m16_rria_simm { export *[const]:2 m16_rria_simm; }

EXT_IS8: val is ext_is_ext=1 & ext_value_1511s & ext_value_1005 & m16_i8_imm [val=(ext_value_1511s << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; }
EXT_IS8: m16_is8_imm is ext_is_ext=0 & m16_is8_imm { tmp:1 = m16_is8_imm; tmpa:2 = sext(tmp); export *[const]:2 tmpa; }
EXT_IS8L3: val is ext_is_ext=0 & ext_value_1511 & ext_value_1005 & m16_is8_imm [val = m16_is8_imm << 3; ] { tmp:2 = val; export *[const]:2 tmp; }
EXT_IS8: m16_is8_imm is ext_is_ext=0 & m16_is8_imm { export *[const]:2 m16_is8_imm; }
EXT_IS8L3: val is ext_is_ext=0 & ext_value_1511 & ext_value_1005 & m16_is8_imm [val = m16_is8_imm << 3; ] { export *[const]:2 val; }

EXT_IU8: val is ext_is_ext=1 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; }
EXT_IU8: val is ext_is_ext=0 & m16_iu8_imm [val = m16_iu8_imm << 2; ] { export *[const]:2 val; }
Expand All @@ -153,7 +153,7 @@ EXT_SHIFT: ext_value_sa40 is ext_is_ext=1 & ext_value_saz=0 & m16_shft_sa=0 &
EXT_SHIFT: val is ext_is_ext=0 & m16_shft_sa=0 [val = 8; ] { export *[const]:1 val;}
EXT_SHIFT: m16_shft_sa is ext_is_ext=0 & m16_shft_sa { export *[const]:1 m16_shft_sa;}

EXT_SET: val is ext_is_ext=1 & m16_ri_z=0 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { tmp:2 = val; tmpb:4 = sext(tmp); export *[const]:4 tmpb; }
EXT_SET: val is ext_is_ext=1 & m16_ri_z=0 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:4 val; }
EXT_SET: m16_iu8_imm is ext_is_ext=0 & m16_iu8_imm { export *[const]:4 m16_iu8_imm; }

OFF_M16: EXT_IS8(m16_rx) is ext_is_ext=1 & EXT_IS8 & m16_rx { tmp:$(REGSIZE) = m16_rx + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; }
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4 changes: 2 additions & 2 deletions Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc
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Expand Up @@ -284,7 +284,7 @@ REG_B_AS: indexExtWord16_0_16s^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 &
REG_B_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):
REG_B_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):
REG_B_AS: labelCalc is reg16_0_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic
REG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {tmp:1 = indexExtWord16_0_16[0,8]; export *[const]:1 tmp; } # Immediate
REG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 { export *[const]:1 indexExtWord16_0_16; } # Immediate
REG_B_AS: "&"^indexExtWord16_0_16 is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute
REG_B_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;} # Constant
REG_B_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;} # Constant
Expand Down Expand Up @@ -324,7 +324,7 @@ SRC_B_AS: indexExtWord16_0_16s^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 &
SRC_B_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):
SRC_B_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):
SRC_B_AS: labelCalc is src16_8_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic
SRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {tmp:1 = indexExtWord16_0_16[0,8]; export *[const]:1 tmp;} # Immediate
SRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16;} # Immediate
SRC_B_AS: "&"^indexExtWord16_0_16 is src16_8_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute
SRC_B_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; } # Constant
SRC_B_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; } # Constant
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4 changes: 2 additions & 2 deletions Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ XREG_B_AS: indexExtWord16_0_16s^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 &
XREG_B_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn):
XREG_B_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+):
XREG_B_AS: labelCalc is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:1 labelCalc; } # Symbolic
XREG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {tmp:1 = indexExtWord16_0_16[0,8]; export *[const]:1 tmp; } # Immediate
XREG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16; } # Immediate
XREG_B_AS: "&"^indexExtWord16_0_16 is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute
XREG_B_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;} # Constant
XREG_B_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;} # Constant
Expand Down Expand Up @@ -159,7 +159,7 @@ XSRC_B_AS: indexExtWord16_0_16s^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 &
XSRC_B_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn):
XSRC_B_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+):
XSRC_B_AS: labelCalc is src16_8_4=0x0 & as=0x1 & bow=0x1 ; indexExtWord16_0_16s [labelCalc = inst_start + 4 + indexExtWord16_0_16s; ] {export *:1 labelCalc; } # Symbolic
XSRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {tmp:1 = indexExtWord16_0_16[0,8]; export *[const]:1 tmp;} # Immediate
XSRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16;} # Immediate
XSRC_B_AS: "&"^indexExtWord16_0_16 is src16_8_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute
XSRC_B_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; } # Constant
XSRC_B_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; } # Constant
Expand Down

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