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# Cores TG Meeting, July 5, 2021 | ||
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## Attendees | ||
* Davide Schiavonne (OpenHW) | ||
* Rick O'Connor (OpenHW) | ||
* Duncan Bees (OpenHW) | ||
* Gianmarco Ottavi (OpenHW) | ||
* Jérôme Quevremont (Thales) | ||
* Sebastien Jacq (Thales) | ||
* Arjan Bink (Silicon Labs) | ||
* Pascal Gouedo (Dolphin) | ||
* Yoann Pruvost (Dolphin) | ||
* Simon Davidmann (Imperas ) | ||
* Eric Matthews (Simon Fraser University) | ||
* Lesley (Simon Fraser University) | ||
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## CV32E40P update | ||
Pascal Gouedo gave an update on what the continuation project for the CV32E40P. They intend to re-encode and verify the PULP instructions (as decided earlier) and to verify the not yet verified PULP event load, PULP_ZFINX and FPU related parts of the CV32E40P. | ||
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## CV32E40X update | ||
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Arjan Bink gave an update on the CV32E40X. See slides. | ||
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## CVA6 update | ||
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Jérôme Quevremont gave an update on the CVA6. Some discussion on reserving CSRs for 3rd parties (good proposal, but will be recommended, not mandated). See slides. | ||
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## Taiga | ||
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Eric Matthews gave an overview of Taiga, a RISC-V core specifically aimed at achieving good performance on FPGA. |
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