Reserve 16 uarch-specific read-only userspace counters

encoding.h

@@ -77,10 +77,18 @@
     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
   __tmp; })
 
+#define rdtime() ({ unsigned long __tmp; \
+  asm volatile ("rdtime %0" : "=r"(__tmp)); \
+  __tmp; })
+
 #define rdcycle() ({ unsigned long __tmp; \
   asm volatile ("rdcycle %0" : "=r"(__tmp)); \
   __tmp; })
 
+#define rdinstret() ({ unsigned long __tmp; \
+  asm volatile ("rdinstret %0" : "=r"(__tmp)); \
+  __tmp; })
+
 #endif
 
 #endif

inst.chisel

@@ -237,6 +237,22 @@ object CSRs {
   val cycle = 0xc00
   val time = 0xc01
   val instret = 0xc02
+  val uarch0 = 0xc10
+  val uarch1 = 0xc11
+  val uarch2 = 0xc12
+  val uarch3 = 0xc13
+  val uarch4 = 0xc14
+  val uarch5 = 0xc15
+  val uarch6 = 0xc16
+  val uarch7 = 0xc17
+  val uarch8 = 0xc18
+  val uarch9 = 0xc19
+  val uarch10 = 0xc1a
+  val uarch11 = 0xc1b
+  val uarch12 = 0xc1c
+  val uarch13 = 0xc1d
+  val uarch14 = 0xc1e
+  val uarch15 = 0xc1f
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
     res += fflags
@@ -265,6 +281,22 @@ object CSRs {
     res += cycle
     res += time
     res += instret
+    res += uarch0
+    res += uarch1
+    res += uarch2
+    res += uarch3
+    res += uarch4
+    res += uarch5
+    res += uarch6
+    res += uarch7
+    res += uarch8
+    res += uarch9
+    res += uarch10
+    res += uarch11
+    res += uarch12
+    res += uarch13
+    res += uarch14
+    res += uarch15
     res.toArray
   }
 }

parse-opcodes

@@ -82,6 +82,22 @@ csrs = [
   (0xC00, 'cycle'),
   (0xC01, 'time'),
   (0xC02, 'instret'),
+  (0xC10, 'uarch0'),
+  (0xC11, 'uarch1'),
+  (0xC12, 'uarch2'),
+  (0xC13, 'uarch3'),
+  (0xC14, 'uarch4'),
+  (0xC15, 'uarch5'),
+  (0xC16, 'uarch6'),
+  (0xC17, 'uarch7'),
+  (0xC18, 'uarch8'),
+  (0xC19, 'uarch9'),
+  (0xC1A, 'uarch10'),
+  (0xC1B, 'uarch11'),
+  (0xC1C, 'uarch12'),
+  (0xC1D, 'uarch13'),
+  (0xC1E, 'uarch14'),
+  (0xC1F, 'uarch15'),
 ]
 
 opcode_base = 0