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Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
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@JyotsnaVerma
JyotsnaVerma committed May 10, 2013
1 parent ed9fc9b commit 1a35b8e
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Showing 9 changed files with 198 additions and 703 deletions.
6 changes: 3 additions & 3 deletions lib/Target/Hexagon/Hexagon.td
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Original file line number Diff line number Diff line change
Expand Up @@ -126,9 +126,9 @@ def getPredNewOpcode : InstrMapping {
def getNewValueOpcode : InstrMapping {
let FilterClass = "NewValueRel";
let RowFields = ["BaseOpcode", "PredSense", "PNewValue"];
let ColFields = ["isNVStore"];
let KeyCol = ["0"];
let ValueCols = [["1"]];
let ColFields = ["NValueST"];
let KeyCol = ["false"];
let ValueCols = [["true"]];
}

def getBasedWithImmOffset : InstrMapping {
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54 changes: 40 additions & 14 deletions lib/Target/Hexagon/HexagonFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -174,30 +174,56 @@ void HexagonFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock::iterator MBBI = prior(MBB.end());
DebugLoc dl = MBBI->getDebugLoc();
//
// Only insert deallocframe if we need to.
// Only insert deallocframe if we need to. Also at -O0. See comment
// in emitPrologue above.
//
if (hasFP(MF)) {
if (hasFP(MF) || MF.getTarget().getOptLevel() == CodeGenOpt::None) {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineBasicBlock::iterator MBBI_end = MBB.end();
//
// For Hexagon, we don't need the frame size.
//
MachineFrameInfo *MFI = MF.getFrameInfo();
int NumBytes = (int) MFI->getStackSize();

const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();

// Handle EH_RETURN.
if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) {
MachineOperand &OffsetReg = MBBI->getOperand(0);
assert(OffsetReg.isReg() && "Offset should be in register!");
BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
BuildMI(MBB, MBBI, dl, TII.get(Hexagon::ADD_rr),
Hexagon::R29).addReg(Hexagon::R29).addReg(Hexagon::R28);
return;
}
// Replace 'jumpr r31' instruction with dealloc_return for V4 and higher
// versions.
if (STI.hasV4TOps() && MBBI->getOpcode() == Hexagon::JMPret
&& !DisableDeallocRet) {
// Remove jumpr node.
MBB.erase(MBBI);
// Check for RESTORE_DEALLOC_RET_JMP_V4 call. Don't emit an extra DEALLOC
// instruction if we encounter it.
MachineBasicBlock::iterator BeforeJMPR =
MBB.begin() == MBBI ? MBBI : prior(MBBI);
if (BeforeJMPR != MBBI &&
BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
// Remove the JMPR node.
MBB.erase(MBBI);
return;
}

// Add dealloc_return.
BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4))
.addImm(NumBytes);
} else { // Add deallocframe for V2 and V3.
BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4));
// Transfer the function live-out registers.
MIB->copyImplicitOps(*MBB.getParent(), &*MBBI);
// Remove the JUMPR node.
MBB.erase(MBBI);
} else { // Add deallocframe for V2 and V3, and V4 tail calls.
// Check for RESTORE_DEALLOC_BEFORE_TAILCALL_V4. We don't need an extra
// DEALLOCFRAME instruction after it.
MachineBasicBlock::iterator Term = MBB.getFirstTerminator();
MachineBasicBlock::iterator I =
Term == MBB.begin() ? MBB.end() : prior(Term);
if (I != MBB.end() &&
I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
return;

BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
}
}
}
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2 changes: 2 additions & 0 deletions lib/Target/Hexagon/HexagonInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -158,6 +158,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
string CextOpcode = "";
string PredSense = "";
string PNewValue = "";
string NValueST = ""; // Set to "true" for new-value stores.
string InputType = ""; // Input is "imm" or "reg" type.
string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
string isFloat = "false"; // Set to "true" for the floating-point load/store.
Expand All @@ -166,6 +167,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
"");
let PNewValue = !if(isPredicatedNew, "new", "");
let NValueST = !if(isNVStore, "true", "false");

// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
}
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147 changes: 42 additions & 105 deletions lib/Target/Hexagon/HexagonInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -630,111 +630,6 @@ bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
return MI->getDesc().isBranch();
}

bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: return false;
// Store Byte
case Hexagon::STrib_nv_V4:
case Hexagon::STrib_indexed_nv_V4:
case Hexagon::STrib_indexed_shl_nv_V4:
case Hexagon::STrib_shl_nv_V4:
case Hexagon::STb_GP_nv_V4:
case Hexagon::POST_STbri_nv_V4:
case Hexagon::STrib_cPt_nv_V4:
case Hexagon::STrib_cdnPt_nv_V4:
case Hexagon::STrib_cNotPt_nv_V4:
case Hexagon::STrib_cdnNotPt_nv_V4:
case Hexagon::STrib_indexed_cPt_nv_V4:
case Hexagon::STrib_indexed_cdnPt_nv_V4:
case Hexagon::STrib_indexed_cNotPt_nv_V4:
case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
case Hexagon::STrib_indexed_shl_cPt_nv_V4:
case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
case Hexagon::POST_STbri_cPt_nv_V4:
case Hexagon::POST_STbri_cdnPt_nv_V4:
case Hexagon::POST_STbri_cNotPt_nv_V4:
case Hexagon::POST_STbri_cdnNotPt_nv_V4:
case Hexagon::STb_GP_cPt_nv_V4:
case Hexagon::STb_GP_cNotPt_nv_V4:
case Hexagon::STb_GP_cdnPt_nv_V4:
case Hexagon::STb_GP_cdnNotPt_nv_V4:
case Hexagon::STrib_abs_nv_V4:
case Hexagon::STrib_abs_cPt_nv_V4:
case Hexagon::STrib_abs_cdnPt_nv_V4:
case Hexagon::STrib_abs_cNotPt_nv_V4:
case Hexagon::STrib_abs_cdnNotPt_nv_V4:

// Store Halfword
case Hexagon::STrih_nv_V4:
case Hexagon::STrih_indexed_nv_V4:
case Hexagon::STrih_indexed_shl_nv_V4:
case Hexagon::STrih_shl_nv_V4:
case Hexagon::STh_GP_nv_V4:
case Hexagon::POST_SThri_nv_V4:
case Hexagon::STrih_cPt_nv_V4:
case Hexagon::STrih_cdnPt_nv_V4:
case Hexagon::STrih_cNotPt_nv_V4:
case Hexagon::STrih_cdnNotPt_nv_V4:
case Hexagon::STrih_indexed_cPt_nv_V4:
case Hexagon::STrih_indexed_cdnPt_nv_V4:
case Hexagon::STrih_indexed_cNotPt_nv_V4:
case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
case Hexagon::STrih_indexed_shl_cPt_nv_V4:
case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
case Hexagon::POST_SThri_cPt_nv_V4:
case Hexagon::POST_SThri_cdnPt_nv_V4:
case Hexagon::POST_SThri_cNotPt_nv_V4:
case Hexagon::POST_SThri_cdnNotPt_nv_V4:
case Hexagon::STh_GP_cPt_nv_V4:
case Hexagon::STh_GP_cNotPt_nv_V4:
case Hexagon::STh_GP_cdnPt_nv_V4:
case Hexagon::STh_GP_cdnNotPt_nv_V4:
case Hexagon::STrih_abs_nv_V4:
case Hexagon::STrih_abs_cPt_nv_V4:
case Hexagon::STrih_abs_cdnPt_nv_V4:
case Hexagon::STrih_abs_cNotPt_nv_V4:
case Hexagon::STrih_abs_cdnNotPt_nv_V4:

// Store Word
case Hexagon::STriw_nv_V4:
case Hexagon::STriw_indexed_nv_V4:
case Hexagon::STriw_indexed_shl_nv_V4:
case Hexagon::STriw_shl_nv_V4:
case Hexagon::STw_GP_nv_V4:
case Hexagon::POST_STwri_nv_V4:
case Hexagon::STriw_cPt_nv_V4:
case Hexagon::STriw_cdnPt_nv_V4:
case Hexagon::STriw_cNotPt_nv_V4:
case Hexagon::STriw_cdnNotPt_nv_V4:
case Hexagon::STriw_indexed_cPt_nv_V4:
case Hexagon::STriw_indexed_cdnPt_nv_V4:
case Hexagon::STriw_indexed_cNotPt_nv_V4:
case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
case Hexagon::STriw_indexed_shl_cPt_nv_V4:
case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
case Hexagon::POST_STwri_cPt_nv_V4:
case Hexagon::POST_STwri_cdnPt_nv_V4:
case Hexagon::POST_STwri_cNotPt_nv_V4:
case Hexagon::POST_STwri_cdnNotPt_nv_V4:
case Hexagon::STw_GP_cPt_nv_V4:
case Hexagon::STw_GP_cNotPt_nv_V4:
case Hexagon::STw_GP_cdnPt_nv_V4:
case Hexagon::STw_GP_cdnNotPt_nv_V4:
case Hexagon::STriw_abs_nv_V4:
case Hexagon::STriw_abs_cPt_nv_V4:
case Hexagon::STriw_abs_cdnPt_nv_V4:
case Hexagon::STriw_abs_cNotPt_nv_V4:
case Hexagon::STriw_abs_cdnNotPt_nv_V4:
return true;
}
}

bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
if (isNewValueJump(MI))
return true;
Expand Down Expand Up @@ -862,6 +757,18 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
}
}

// New Value Store instructions.
bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
const uint64_t F = MI->getDesc().TSFlags;

return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
}

bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
const uint64_t F = get(Opcode).TSFlags;

return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
}

int HexagonInstrInfo::
getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
Expand Down Expand Up @@ -1304,6 +1211,8 @@ isValidAutoIncImm(const EVT VT, const int Offset) const {

bool HexagonInstrInfo::
isMemOp(const MachineInstr *MI) const {
// return MI->getDesc().mayLoad() && MI->getDesc().mayStore();

switch (MI->getOpcode())
{
default: return false;
Expand Down Expand Up @@ -1611,6 +1520,34 @@ bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
(isPredicated(MI) && isPredicatedNew(MI)));
}

// Return the new value instruction for a given store.
int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
if (NVOpcode >= 0) // Valid new-value store instruction.
return NVOpcode;

switch (MI->getOpcode()) {
default: llvm_unreachable("Unknown .new type");
// store new value byte
case Hexagon::STrib_shl_V4:
return Hexagon::STrib_shl_nv_V4;

case Hexagon::STrih_shl_V4:
return Hexagon::STrih_shl_nv_V4;

case Hexagon::STriw_f:
return Hexagon::STriw_nv_V4;

case Hexagon::STriw_indexed_f:
return Hexagon::STriw_indexed_nv_V4;

case Hexagon::STriw_shl_V4:
return Hexagon::STriw_shl_nv_V4;

}
return 0;
}

// Return .new predicate version for an instruction.
int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
const MachineBranchProbabilityInfo
Expand Down
2 changes: 2 additions & 0 deletions lib/Target/Hexagon/HexagonInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -185,6 +185,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
bool isNewValueInst(const MachineInstr* MI) const;
bool isNewValue(const MachineInstr* MI) const;
bool isDotNewInst(const MachineInstr* MI) const;
int GetDotNewOp(const MachineInstr* MI) const;
int GetDotNewPredOp(MachineInstr *MI,
const MachineBranchProbabilityInfo
*MBPI) const;
Expand All @@ -194,6 +195,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
bool isExtended(const MachineInstr* MI) const;
bool isPostIncrement(const MachineInstr* MI) const;
bool isNewValueStore(const MachineInstr* MI) const;
bool isNewValueStore(unsigned Opcode) const;
bool isNewValueJump(const MachineInstr* MI) const;
bool isNewValueJumpCandidate(const MachineInstr *MI) const;

Expand Down
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