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Extensions of Hexagon V4 instructions.
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This adds new instructions for Hexagon V4 architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
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Sirish Pande committed May 3, 2012
1 parent a199e01 commit 71d5646
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Showing 9 changed files with 4,341 additions and 1,573 deletions.
6 changes: 3 additions & 3 deletions lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -375,7 +375,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
};
ReplaceUses(Froms, Tos, 3);
return Result_2;
}
}
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
Expand Down Expand Up @@ -723,7 +723,7 @@ SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
if (AM != ISD::UNINDEXED) {
return SelectIndexedStore(ST, dl);
}

return SelectBaseOffsetStore(ST, dl);
}

Expand Down Expand Up @@ -1215,7 +1215,7 @@ SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {

// Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
// Rd and Rd' are assigned to the same register
SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_rr_acc, dl, MVT::i32,
SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_ADD_rr, dl, MVT::i32,
N->getOperand(1),
Src1->getOperand(0),
Src1->getOperand(1));
Expand Down
136 changes: 108 additions & 28 deletions lib/Target/Hexagon/HexagonInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -13,29 +13,48 @@
// *** Must match HexagonBaseInfo.h ***
//===----------------------------------------------------------------------===//

class Type<bits<5> t> {
bits<5> Value = t;
}
def TypePSEUDO : Type<0>;
def TypeALU32 : Type<1>;
def TypeCR : Type<2>;
def TypeJR : Type<3>;
def TypeJ : Type<4>;
def TypeLD : Type<5>;
def TypeST : Type<6>;
def TypeSYSTEM : Type<7>;
def TypeXTYPE : Type<8>;
def TypeMARKER : Type<31>;

//===----------------------------------------------------------------------===//
// Intruction Class Declaration +
//===----------------------------------------------------------------------===//

class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr, InstrItinClass itin> : Instruction {
string cstr, InstrItinClass itin, Type type> : Instruction {
field bits<32> Inst;

let Namespace = "Hexagon";

dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let AsmString = asmstr;
let Pattern = pattern;
let Constraints = cstr;
let Itinerary = itin;

// *** The code below must match HexagonBaseInfo.h ***

let Itinerary = itin;
let Size = 4;

// *** Must match HexagonBaseInfo.h ***
// Instruction type according to the ISA.
Type HexagonType = type;
let TSFlags{4-0} = HexagonType.Value;
// Solo instructions, i.e., those that cannot be in a packet with others.
bits<1> isHexagonSolo = 0;
let TSFlags{5} = isHexagonSolo;
// Predicated instructions.
bits<1> isPredicated = 0;
let TSFlags{1} = isPredicated;
let TSFlags{6} = isPredicated;

// *** The code above must match HexagonBaseInfo.h ***
}
Expand All @@ -47,17 +66,25 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
// LD Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", LD> {
: InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
bits<5> rd;
bits<5> rs;
bits<13> imm13;
}

class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
bits<5> rd;
bits<5> rs;
bits<13> imm13;
let mayLoad = 1;
}

// LD Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: InstHexagon<outs, ins, asmstr, pattern, cstr, LD> {
: InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
Expand All @@ -68,7 +95,24 @@ class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
// ST Instruction Class in V4 can take SLOT0 & SLOT1.
// Definition of the instruction class CHANGED from V2/V3 to V4.
class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", ST> {
: InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
bits<5> rd;
bits<5> rs;
bits<13> imm13;
}

class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
bits<5> rd;
bits<5> rs;
bits<13> imm13;
let mayStore = 1;
}

// SYSTEM Instruction Class in V4 can take SLOT0 only
// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {
bits<5> rd;
bits<5> rs;
bits<13> imm13;
Expand All @@ -79,7 +123,7 @@ class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
// Definition of the instruction class CHANGED from V2/V3 to V4.
class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: InstHexagon<outs, ins, asmstr, pattern, cstr, ST> {
: InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
Expand All @@ -89,7 +133,7 @@ class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
// ALU32 Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", ALU32> {
: InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
Expand All @@ -102,7 +146,17 @@ class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
// Definition of the instruction class NOT CHANGED.
// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", ALU64> {
: InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
bits<16> imm16;
bits<16> imm16_2;
}

class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
Expand All @@ -115,7 +169,7 @@ class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
// Definition of the instruction class NOT CHANGED.
// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", M> {
: InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
Expand All @@ -126,8 +180,8 @@ class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
// Definition of the instruction class NOT CHANGED.
// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: InstHexagon<outs, ins, asmstr, pattern, cstr, M> {
string cstr>
: InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
Expand All @@ -138,9 +192,7 @@ class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
// Definition of the instruction class NOT CHANGED.
// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
//: InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, M)> {
: InstHexagon<outs, ins, asmstr, pattern, "", S> {
// : InstHexagon<outs, ins, asmstr, pattern, "", S> {
: InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
Expand All @@ -151,8 +203,8 @@ class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
// Definition of the instruction class NOT CHANGED.
// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
string cstr>
: InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
// : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
// : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
bits<5> rd;
Expand All @@ -163,30 +215,37 @@ class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
// J Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", J> {
: InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {
bits<16> imm16;
}

// JR Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", JR> {
: InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {
bits<5> rs;
bits<5> pu; // Predicate register
}

// CR Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", CR> {
: InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {
bits<5> rs;
bits<10> imm10;
}

class Marker<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {
let isCodeGenOnly = 1;
let isPseudo = 1;
}

class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>;

: InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {
let isCodeGenOnly = 1;
let isPseudo = 1;
}

//===----------------------------------------------------------------------===//
// Intruction Classes Definitions -
Expand Down Expand Up @@ -222,6 +281,11 @@ class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
: ALU64Type<outs, ins, asmstr, pattern> {
}

class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
: ALU64Type<outs, ins, asmstr, pattern> {
let rt{0-4} = 0;
}

// J Type Instructions.
class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
: JType<outs, ins, asmstr, pattern> {
Expand All @@ -234,15 +298,31 @@ class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>


// Post increment ST Instruction.
class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: STInstPost<outs, ins, asmstr, pattern, cstr> {
let rt{0-4} = 0;
}

class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: STInstPost<outs, ins, asmstr, pattern, cstr> {
let rt{0-4} = 0;
let mayStore = 1;
}

// Post increment LD Instruction.
class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: LDInstPost<outs, ins, asmstr, pattern, cstr> {
let rt{0-4} = 0;
}

class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: LDInstPost<outs, ins, asmstr, pattern, cstr> {
let rt{0-4} = 0;
let mayLoad = 1;
}

//===----------------------------------------------------------------------===//
Expand Down
27 changes: 24 additions & 3 deletions lib/Target/Hexagon/HexagonInstrFormatsV4.td
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Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,25 @@
//
//===----------------------------------------------------------------------===//

//----------------------------------------------------------------------------//
// Hexagon Intruction Flags +
//
// *** Must match BaseInfo.h ***
//----------------------------------------------------------------------------//

def TypeMEMOP : Type<9>;
def TypeNV : Type<10>;
def TypePREFIX : Type<30>;

//----------------------------------------------------------------------------//
// Intruction Classes Definitions +
//----------------------------------------------------------------------------//

//
// NV type instructions.
//
class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", NV_V4> {
: InstHexagon<outs, ins, asmstr, pattern, "", NV_V4, TypeNV> {
bits<5> rd;
bits<5> rs;
bits<13> imm13;
Expand All @@ -24,7 +38,7 @@ class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
// Definition of Post increment new value store.
class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
string cstr>
: InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4> {
: InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
Expand All @@ -39,8 +53,15 @@ class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
}

class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4> {
: InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4, TypeMEMOP> {
bits<5> rd;
bits<5> rs;
bits<6> imm6;
}

class Immext<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX> {
let isCodeGenOnly = 1;

bits<26> imm26;
}
7 changes: 0 additions & 7 deletions lib/Target/Hexagon/HexagonInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1200,9 +1200,6 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
case Hexagon::LDriub:
return !invertPredicate ? Hexagon::LDriub_cPt :
Hexagon::LDriub_cNotPt;
case Hexagon::LDriubit:
return !invertPredicate ? Hexagon::LDriub_cPt :
Hexagon::LDriub_cNotPt;
// Load Indexed.
case Hexagon::LDrid_indexed:
return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
Expand Down Expand Up @@ -1409,17 +1406,13 @@ isValidOffset(const int Opcode, const int Offset) const {
case Hexagon::LDrih:
case Hexagon::LDriuh:
case Hexagon::STrih:
case Hexagon::LDrih_ae:
assert((Offset % 2 == 0) && "Offset has incorrect alignment");
return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
(Offset <= Hexagon_MEMH_OFFSET_MAX);

case Hexagon::LDrib:
case Hexagon::STrib:
case Hexagon::LDriub:
case Hexagon::LDriubit:
case Hexagon::LDrib_ae:
case Hexagon::LDriub_ae:
return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
(Offset <= Hexagon_MEMB_OFFSET_MAX);

Expand Down
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