Change all #include'd files to be :: rules instead of : rules

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8019 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SparcV9/Makefile

@@ -48,7 +48,7 @@ TARGET_NAME := SparcV9
 
 TABLEGEN_FILES := $(wildcard *.td)
 
-$(TARGET_NAME)CodeEmitter.inc: $(TABLEGEN_FILES) $(TBLGEN)
+$(TARGET_NAME)CodeEmitter.inc:: $(TABLEGEN_FILES) $(TBLGEN)
 	$(TBLGEN) $(TARGET_NAME).td -gen-emitter -o $@
 
 clean::

lib/Target/X86/Makefile

@@ -7,22 +7,22 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
                  X86GenRegisterInfo.inc X86GenInstrNames.inc \
                  X86GenInstrInfo.inc X86GenInstrSelector.inc
 
-X86GenRegisterNames.inc:  X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
+X86GenRegisterNames.inc::  X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
 	$(TBLGEN) $< -gen-register-enums -o $@
 
-X86GenRegisterInfo.h.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
+X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
 	$(TBLGEN) $< -gen-register-desc-header -o $@
 
-X86GenRegisterInfo.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
+X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
 	$(TBLGEN) $< -gen-register-desc -o $@
 
-X86GenInstrNames.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
+X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
 	$(TBLGEN) $< -gen-instr-enums -o $@
 
-X86GenInstrInfo.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
+X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
 	$(TBLGEN) $< -gen-instr-desc -o $@
 
-X86GenInstrSelector.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
+X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
 	$(TBLGEN) $< -gen-instr-selector -o $@
 
 clean::