Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <[email protected]>

Makefile

@@ -1,7 +1,7 @@
 VERSION = 2015
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME =
 
 # *DOCUMENTATION*
@@ -947,7 +947,9 @@ ifneq ($(CONFIG_X86_RESET_VECTOR),)
 rom: u-boot.rom FORCE
 
 IFDTOOL=$(objtree)/tools/ifdtool
-IFDTOOL_FLAGS  = -w $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin
+IFDTOOL_FLAGS  = -f 0:$(objtree)/u-boot.dtb
+IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
+IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin
 IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
 
 ifneq ($(CONFIG_HAVE_INTEL_ME),)
@@ -956,11 +958,19 @@ IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
 endif
 
 ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
+endif
+
+ifneq ($(CONFIG_HAVE_FSP),)
+IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_CMC),)
+IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
 endif
 
 ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
 endif
 
 quiet_cmd_ifdtool = IFDTOOL $@

README

@@ -1773,6 +1773,15 @@ The following options need to be configured:
 		regarding the non-volatile storage device. Define this to
 		the eMMC device that fastboot should use to store the image.
 
+		CONFIG_FASTBOOT_GPT_NAME
+		The fastboot "flash" command supports writing the downloaded
+		image to the Protective MBR and the Primary GUID Partition
+		Table. (Additionally, this downloaded image is post-processed
+		to generate and write the Backup GUID Partition Table.)
+		This occurs when the specified "partition name" on the
+		"fastboot flash" command line matches this value.
+		Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
+
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
 		CONFIG_JFFS2_NAND_DEV

arch/arm/cpu/armv7/bcm281xx/Makefile

@@ -10,3 +10,4 @@ obj-y	+= clk-bcm281xx.o
 obj-y	+= clk-sdio.o
 obj-y	+= clk-bsc.o
 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y	+= clk-usb-otg.o

arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c

@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
 	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
 };
 
+static struct bus_clk_data usb_otg_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
 static struct bus_clk_data sdio1_ahb_data = {
 	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
 };
@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
  */
 
 /* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+	.clk = {
+		.name = "usb_otg_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &usb_otg_ahb_data,
+};
+
 static struct bus_clock sdio1_ahb_clk = {
 	.clk = {
 		.name = "sdio1_ahb_clk",
@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
 	CLK_LK(bsc2),
 	CLK_LK(bsc3),
 	/* Bus clocks */
+	CLK_LK(usb_otg_ahb),
 	CLK_LK(sdio1_ahb),
 	CLK_LK(sdio2_ahb),
 	CLK_LK(sdio3_ahb),

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case HSOTG_BASE_ADDR:
+		ahbstr = "usb_otg_ahb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	return clk_get_and_enable(ahbstr);
+}

arch/arm/cpu/armv7/kona-common/clk-stubs.c

@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
 {
 	return 0;
 }
+
+int __weak clk_usb_otg_enable(void *base)
+{
+	return 0;
+}

arch/arm/include/asm/arch-bcm281xx/sysmap.h

@@ -13,6 +13,8 @@
 #define ESUB_CLK_BASE_ADDR	0x38000000
 #define ESW_CONTRL_BASE_ADDR	0x38200000
 #define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
 #define KONA_MST_CLK_BASE_ADDR	0x3f001000
 #define KONA_SLV_CLK_BASE_ADDR	0x3e011000
 #define PMU_BSC_BASE_ADDR	0x3500d000

arch/arm/include/asm/arch-bcm2835/mbox.h

@@ -140,6 +140,7 @@ struct bcm2835_mbox_tag_hdr {
 #define BCM2835_BOARD_REV_B_REV2_f	0xf
 #define BCM2835_BOARD_REV_B_PLUS	0x10
 #define BCM2835_BOARD_REV_CM		0x11
+#define BCM2835_BOARD_REV_A_PLUS	0x12
 
 struct bcm2835_mbox_tag_get_board_rev {
 	struct bcm2835_mbox_tag_hdr tag_hdr;

arch/arm/include/asm/kona-common/clk.h

@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
 struct clk *clk_get_parent(struct clk *clk);
 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
 int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
 
 #endif

arch/arm/include/asm/semihosting.h

@@ -12,10 +12,6 @@
  * code for more information.
  */
 int smh_load(const char *fname, void *memp, int avail, int verbose);
-int smh_read(int fd, void *memp, int len);
-int smh_open(const char *fname, char *modestr);
-int smh_close(int fd);
-int smh_len_fd(int fd);
-int smh_len(const char *fname);
+long smh_len(const char *fname);
 
 #endif /* __SEMIHOSTING_H__ */