Merge branch 'master' of git://git.denx.de/u-boot-arm

.gitignore

@@ -44,11 +44,7 @@
 #
 # Generated files
 #
-
 /LOG
-/errlog
-/reloc_off
-
 /spl/
 /tpl/
 

.mailmap

@@ -0,0 +1,27 @@
+#
+# This list is used by git-shortlog to fix a few botched name translations
+# in the git archive, either because the author's full name was messed up
+# and/or not always written the same way, making contributions from the
+# same person appearing not to be so or badly displayed.
+#
+# This file can be modified by hand or updated by the following command:
+#  scripts/mailmapper > tmp; mv tmp .mailmap
+#
+
+Allen Martin <[email protected]>
+Andreas Bießmann <[email protected]>
+Aneesh V <[email protected]>
+Dirk Behme <[email protected]>
+Fabio Estevam <[email protected]>
+Jagannadha Sutradharudu Teki <[email protected]>
+Markus Klotzbuecher <[email protected]>
+Prabhakar Kushwaha <[email protected]>
+Rajeshwari Shinde <[email protected]>
+Sandeep Paulraj <[email protected]>
+Shaohui Xie <[email protected]>
+Stefan Roese <stroese>
+Stefano Babic <[email protected]>
+TsiChung Liew <[email protected]>
+Wolfgang Denk <wdenk>
+York Sun <[email protected]>
+Łukasz Majewski <[email protected]>

Makefile

@@ -915,6 +915,12 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
 u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
 	$(call if_changed,pad_cat)
 
+MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
+u-boot-nand.gph: u-boot.bin FORCE
+	$(call if_changed,mkimage)
+	@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+
 ifneq ($(CONFIG_SUNXI),)
 OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
 				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
@@ -1137,7 +1143,7 @@ spl/sunxi-spl.bin: spl/u-boot-spl
 tpl/u-boot-tpl.bin: tools prepare
 	$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
 
-TAG_SUBDIRS := $(u-boot-dirs) include
+TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
 
 FIND := find
 FINDFLAGS := -L
@@ -1147,7 +1153,7 @@ tags ctags:
 						-name '*.[chS]' -print`
 
 etags:
-		etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
+		etags -a -o etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
 						-name '*.[chS]' -print`
 cscope:
 		$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \
@@ -1222,7 +1228,7 @@ CLOBBER_FILES += u-boot* MLO* SPL System.map
 MRPROPER_DIRS  += include/config include/generated          \
 		  .tmp_objdiff
 MRPROPER_FILES += .config .config.old \
-		  tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
+		  ctags etags cscope* GPATH GTAGS GRTAGS GSYMS \
 		  include/config.h include/config.mk
 
 # clean - Delete most, but leave enough to build external modules
@@ -1311,7 +1317,8 @@ help:
 	@echo  '  dir/file.[oisS] - Build specified target only'
 	@echo  '  dir/file.lst    - Build specified mixed source/assembly target only'
 	@echo  '                    (requires a recent binutils and recent build (System.map))'
-	@echo  '  tags/TAGS	  - Generate tags file for editors'
+	@echo  '  tags/ctags	  - Generate ctags file for editors'
+	@echo  '  etags		  - Generate etags file for editors'
 	@echo  '  cscope	  - Generate cscope index'
 	@echo  '  ubootrelease	  - Output the release version string'
 	@echo  '  ubootversion	  - Output the version stored in Makefile'

README

@@ -3751,6 +3751,22 @@ Configuration Settings:
 - CONFIG_SYS_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
 
+- CONFIG_SYS_MALLOC_F_LEN
+		Size of the malloc() pool for use before relocation. If
+		this is defined, then a very simple malloc() implementation
+		will become available before relocation. The address is just
+		below the global data, and the stack is moved down to make
+		space.
+
+		This feature allocates regions with increasing addresses
+		within the region. calloc() is supported, but realloc()
+		is not available. free() is supported but does nothing.
+		The memory will be freed (or in fact just forgotton) when
+		U-Boot relocates itself.
+
+		Pre-relocation malloc() is only supported on sandbox
+		at present but is fairly easy to enable for other archs.
+
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,

arch/arm/config.mk

@@ -113,7 +113,7 @@ endif
 ifdef CONFIG_ARM64
 OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
-OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
 endif
 
 ifdef CONFIG_OF_EMBED

arch/arm/cpu/armv7/Makefile

@@ -21,6 +21,11 @@ endif
 ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
 obj-y	+= nonsec_virt.o
 obj-y	+= virt-v7.o
+obj-y	+= virt-dt.o
+endif
+
+ifneq ($(CONFIG_ARMV7_PSCI),)
+obj-y	+= psci.o
 endif
 
 obj-$(CONFIG_KONA) += kona-common/

arch/arm/cpu/armv7/keystone/Makefile

@@ -8,9 +8,12 @@
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o
+obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
 obj-y	+= cmd_clock.o
 obj-y	+= cmd_mon.o
-obj-y	+= keystone_nav.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y	+= msmc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 obj-y	+= ddr3.o
+obj-y	+= keystone.o

arch/arm/cpu/armv7/keystone/clock-k2e.c

@@ -0,0 +1,101 @@
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case DDR3_PLL:
+			ret = external_clk[ddr3_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:      return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
+	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}

arch/arm/cpu/armv7/keystone/clock-k2hk.c

@@ -0,0 +1,113 @@
+/*
+ * Keystone2: get clk rate for K2HK
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL]	= {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL]	= {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				 PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case TETRIS_PLL:
+			ret = external_clk[tetris_clk];
+			reg = KS2_ARMPLLCTL0;
+			break;
+		case DDR3A_PLL:
+			ret = external_clk[ddr3a_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		case DDR3B_PLL:
+			ret = external_clk[ddr3b_clk];
+			reg = KS2_DDR3BPLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:	return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
+	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
+	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
+	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}