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[AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
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Fixes Bug 28215. Lit tests updated.

Differential Revision: https://reviews.llvm.org/D25837

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284825 91177308-0d34-0410-b5e6-96231b3b80d8
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@atamazov
atamazov committed Oct 21, 2016
1 parent f8de69b commit 3398735
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Showing 3 changed files with 24 additions and 24 deletions.
8 changes: 4 additions & 4 deletions lib/Target/AMDGPU/DSInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -247,6 +247,8 @@ def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;

let mayLoad = 0 in {
def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
Expand All @@ -259,8 +261,6 @@ def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
def DS_MIN_F32 : DS_1A2D_NORET<"ds_min_f32">;
def DS_MAX_F32 : DS_1A2D_NORET<"ds_max_f32">;

def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
Expand Down Expand Up @@ -317,9 +317,9 @@ def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
AtomicNoRet<"ds_cmpst_b32", 1>;
def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
AtomicNoRet<"ds_cmpst_f32", 1>;
def DS_MIN_RTN_F32 : DS_1A2D_RET <"ds_min_rtn_f32">,
def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
AtomicNoRet<"ds_min_f32", 1>;
def DS_MAX_RTN_F32 : DS_1A2D_RET <"ds_max_rtn_f32">,
def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
AtomicNoRet<"ds_max_f32", 1>;

def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
Expand Down
24 changes: 12 additions & 12 deletions test/MC/AMDGPU/ds.s
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Original file line number Diff line number Diff line change
Expand Up @@ -131,13 +131,13 @@ ds_cmpst_f32 v2, v4, v6
// SICI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x06,0x00]
// VI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x22,0xd8,0x02,0x04,0x06,0x00]

ds_min_f32 v2, v4, v6
// SICI: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x06,0x00]
// VI: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x06,0x00]
ds_min_f32 v2, v4
// SICI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00]

ds_max_f32 v2, v4, v6
// SICI: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x06,0x00]
// VI: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x06,0x00]
ds_max_f32 v2, v4
// SICI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]

ds_gws_init v2 gds
// SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00]
Expand Down Expand Up @@ -243,13 +243,13 @@ ds_cmpst_rtn_f32 v8, v2, v4, v6
// SICI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc4,0xd8,0x02,0x04,0x06,0x08]
// VI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x62,0xd8,0x02,0x04,0x06,0x08]

ds_min_rtn_f32 v8, v2, v4, v6
// SICI: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc8,0xd8,0x02,0x04,0x06,0x08]
// VI: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x06,0x08]
ds_min_rtn_f32 v8, v2, v4
// SICI: ds_min_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0xc8,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_min_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x00,0x08]

ds_max_rtn_f32 v8, v2, v4, v6
// SICI: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x06,0x08]
// VI: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x06,0x08]
ds_max_rtn_f32 v8, v2, v4
// SICI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x00,0x08]

ds_swizzle_b32 v8, v2
// SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
Expand Down
16 changes: 8 additions & 8 deletions test/MC/Disassembler/AMDGPU/ds_vi.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -75,11 +75,11 @@
# VI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x22,0xd8,0x02,0x04,0x06,0x00]
0x00 0x00 0x22 0xd8 0x02 0x04 0x06 0x00

# VI: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x06,0x00]
0x00 0x00 0x24 0xd8 0x02 0x04 0x06 0x00
# VI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00]
0x00 0x00 0x24 0xd8 0x02 0x04 0x00 0x00

# VI: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x06,0x00]
0x00 0x00 0x26 0xd8 0x02 0x04 0x06 0x00
# VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
0x00 0x00 0x26 0xd8 0x02 0x04 0x00 0x00

# VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
0x00 0x00 0x33 0xd8 0x02 0x00 0x00 0x00
Expand Down Expand Up @@ -156,11 +156,11 @@
# VI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x62,0xd8,0x02,0x04,0x06,0x08]
0x00 0x00 0x62 0xd8 0x02 0x04 0x06 0x08

# VI: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x06,0x08]
0x00 0x00 0x64 0xd8 0x02 0x04 0x06 0x08
# VI: ds_min_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x00,0x08]
0x00 0x00 0x64 0xd8 0x02 0x04 0x00 0x08

# VI: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x06,0x08]
0x00 0x00 0x66 0xd8 0x02 0x04 0x06 0x08
# VI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x00,0x08]
0x00 0x00 0x66 0xd8 0x02 0x04 0x00 0x08

# VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08
Expand Down

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