verilator: Enhance testbench to verify output and return with appropr…

…iate error codes.
diegob94 · Dec 1, 2017 · 7c769aa · 7c769aa
1 parent 24a3c08
commit 7c769aa
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Showing 3 changed files with 60 additions and 14 deletions.
diff --git a/verif/verilator/Makefile b/verif/verilator/Makefile
@@ -25,10 +25,10 @@ $(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/VNV_nvdla: $(DEPTH)/$(OUTDIR)/$(PROJECT)
 	cp nvdla.cpp $(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/nvdla.cpp
 	make -C $(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator -f VNV_nvdla.mk CC=$(CLANG) CXX=$(CLANG)++ VM_PARALLEL_BUILDS=1
 
-$(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/test/%: $(DEPTH)/verif/traces/traceplayer/%
+$(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/test/%/trace.bin: $(DEPTH)/verif/traces/traceplayer/% input_txn_to_verilator.pl
 	rm -rf $@
-	mkdir -p $@
-	$(PERL) input_txn_to_verilator.pl $< $@/trace.bin
+	mkdir -p $(dir $@)
+	$(PERL) input_txn_to_verilator.pl $< $@
 
-run: $(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/test/$(TEST) $(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/VNV_nvdla
+run: $(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/test/$(TEST)/trace.bin $(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/VNV_nvdla
 	cd $(DEPTH)/$(OUTDIR)/$(PROJECT)/verilator/test/$(TEST) && ../../VNV_nvdla trace.bin
diff --git a/verif/verilator/input_txn_to_verilator.pl b/verif/verilator/input_txn_to_verilator.pl
@@ -105,21 +105,19 @@
       $exp_data = $values[3];
 
       print $ouf pack("CLLL", 3, hex($address), hex($bitmask), hex($exp_data));
-    } elsif ($values[0] =~ /dump_mem/) {
-      my $addr = $values[1];
-      my $offset = $values[2];
-      my $mem_out = $values[3];
-
-      print $ouf pack("CLLL", 4, hex($addr), hex($offset), length($mem_out)) . $mem_out;
-    } elsif ($values[0] =~ /load_mem/) {
+    } elsif ($values[0] =~ /(load|dump)_mem/) {
       my $addr = $values[1];
       my $offset = $values[2];
       my $mem_in = $values[3];
       my $raw_file;
       my $mem_out;
       my $minf, my $mouf;
+      my $cmd;
+
+      $cmd = 5 if ($values[0] =~ /load_mem/);
+      $cmd = 4 if ($values[0] =~ /dump_mem/);
 
-      print $ouf pack("CLL", 5, hex($addr), hex($offset));
+      print $ouf pack("CLL", $cmd, hex($addr), hex($offset));
       open $minf, "<". "$test_dir/$mem_in";
 
       print "File $load_file_counter $addr $offset\n";
@@ -151,8 +149,12 @@
       else {
         die "only .dat files supported in this tool so far";
       }
-
+      
       close $minf;
+
+      if ($values[0] =~ /dump_mem/) {
+       print $ouf pack("L", length($mem_in)) . $mem_in;
+      }
     }
 #print " HexString: $hex_string" . "\n";
 #my @split_hex = ($hex_string =~ m/../g);

diff --git a/verif/verilator/nvdla.cpp b/verif/verilator/nvdla.cpp
@@ -49,11 +49,14 @@ class CSBMaster {
 
 	VNV_nvdla *dla;
 
+	int _test_passed;
+
 public:
 	CSBMaster(VNV_nvdla *_dla) {
 		dla = _dla;
 
 		dla->csb2nvdla_valid = 0;
+		_test_passed = 1;
 	}
 
 	void read(uint32_t addr, uint32_t mask, uint32_t data) {
@@ -114,6 +117,7 @@ class CSBMaster {
 				printf("(%lu) invalid response -- trying again\n", ticks);
 				if (!op.tries) {
 					printf("(%lu) ERROR: timed out reading response\n", ticks);
+					_test_passed = 0;
 					opq.pop();
 				}
 			} else
@@ -154,6 +158,10 @@ class CSBMaster {
 	bool done() {
 		return opq.empty();
 	}
+
+	int test_passed() {
+		return _test_passed;
+	}
 };
 
 template <typename ADDRTYPE>
@@ -441,6 +449,8 @@ class TraceLoader {
 
 	CSBMaster *csb;
 	AXIResponder<uint64_t> *axi_dbb, *axi_cvsram;
+
+	int _test_passed;
 
 public:
 	enum stop_type {	
@@ -453,6 +463,7 @@ class TraceLoader {
 		csb = _csb;
 		axi_dbb = _axi_dbb;
 		axi_cvsram = _axi_cvsram;
+		_test_passed = 1;
 	}
 
 	void load(const char *fname) {
@@ -499,12 +510,16 @@ class TraceLoader {
 			case 4: {
 				uint32_t addr;
 				uint32_t len;
+				uint8_t *buf;
 				uint32_t namelen;
 				char *fname;
 				axi_op op;
 
 				VERILY_READ(&addr, 4);
 				VERILY_READ(&len, 4);
+				buf = (uint8_t *)malloc(len);
+				VERILY_READ(buf, len);
+
 				VERILY_READ(&namelen, 4);
 				fname = (char *) malloc(namelen+1);
 				VERILY_READ(fname, namelen);
@@ -513,6 +528,7 @@ class TraceLoader {
 				op.opcode = AXI_DUMPMEM;
 				op.addr = addr;
 				op.len = len;
+				op.buf = buf;
 				op.fname = fname;
 				opq.push(op);
 				csb->ext_event(TRACE_AXIEVENT);
@@ -586,6 +602,8 @@ class TraceLoader {
 		}
 		case AXI_DUMPMEM: {
 			int fd;
+			const uint8_t *buf = op.buf;
+			int matched = 1;
 
 			printf("AXI: dumping memory to %s\n", op.fname);
 			fd = creat(op.fname, 0666);
@@ -596,11 +614,19 @@ class TraceLoader {
 			while (op.len) {
 				uint8_t da = axi->read(op.addr);
 				write(fd, &da, 1);
-
+				if (da != *buf && matched) {
+					printf("AXI: FAIL: mismatch at memory address %08x (exp 0x%02x, got 0x%02x), and maybe others too\n", op.addr, *buf, da);
+					matched = 0;
+					_test_passed = 0;
+				}
+				buf++;
 				op.addr++;
 				op.len--;
 			}
 			close(fd);
+
+			if (matched)
+				printf("AXI: memory dump matched reference\n");
 			break;
 		}
 		default:
@@ -609,6 +635,10 @@ class TraceLoader {
 
 		opq.pop();
 	}
+
+	int test_passed() {
+		return _test_passed;
+	}
 };
 
 int main(int argc, const char **argv, char **env) {
@@ -812,4 +842,18 @@ int main(int argc, const char **argv, char **env) {
 	}
 
 	printf("done at %lu ticks\n", ticks);
+
+	if (!trace->test_passed()) {
+		printf("*** FAIL: test failed due to output mismatch\n");
+		return 1;
+	}
+
+	if (!csb->test_passed()) {
+		printf("*** FAIL: test failed due to CSB read mismatch\n");
+		return 2;
+	}
+
+	printf("*** PASS\n");
+
+	return 0;
 }