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ARM: Remove dependency of plat-orion GPIO code on mach directory incl…
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…udes.

This patch makes the various mach dirs that use the plat-orion GPIO
code pass in GPIO-related platform info (GPIO controller base address,
secondary base IRQ number, etc) explicitly, instead of having
plat-orion get those values by including a mach dir include file --
the latter mechanism is problematic if you want to support multiple
ARM platforms in the same kernel image.

Signed-off-by: Lennert Buytenhek <[email protected]>
Signed-off-by: Nicolas Pitre <[email protected]>
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@buytenh @npitre
buytenh authored and npitre committed Mar 3, 2011
1 parent 4ee1f6b commit 9eac6d0
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Showing 17 changed files with 348 additions and 352 deletions.
3 changes: 2 additions & 1 deletion arch/arm/mach-dove/include/mach/dove.h
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Expand Up @@ -130,7 +130,8 @@
#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
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42 changes: 0 additions & 42 deletions arch/arm/mach-dove/include/mach/gpio.h
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Expand Up @@ -6,46 +6,4 @@
* warranty of any kind, whether express or implied.
*/

#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H

#include <asm/errno.h>
#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */

#define GPIO_MAX 72

#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)

#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \
((pin < 64) ? GPIO_BASE_HI : \
DOVE_GPIO2_VIRT_BASE))

#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)
#define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08)
#define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c)
#define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10)
#define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14)
#define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18)
#define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c)

static inline int gpio_to_irq(int pin)
{
if (pin < NR_GPIO_IRQS)
return pin + IRQ_DOVE_GPIO_START;

return -EINVAL;
}

static inline int irq_to_gpio(int irq)
{
if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
return irq - IRQ_DOVE_GPIO_START;

return -EINVAL;
}

#endif
30 changes: 14 additions & 16 deletions arch/arm/mach-dove/irq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -99,30 +99,28 @@ void __init dove_init_irq(void)
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));

/*
* Mask and clear GPIO IRQ interrupts.
* Initialize gpiolib for GPIOs 0-71.
*/
writel(0, GPIO_LEVEL_MASK(0));
writel(0, GPIO_EDGE_MASK(0));
writel(0, GPIO_EDGE_CAUSE(0));
orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START);
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);

orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 32);
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);

orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 64);

/*
* Mask and clear PMU interrupts
*/
writel(0, PMU_INTERRUPT_MASK);
writel(0, PMU_INTERRUPT_CAUSE);

for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);

for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
set_irq_chip(i, &pmu_irq_chip);
set_irq_handler(i, handle_level_irq);
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29 changes: 0 additions & 29 deletions arch/arm/mach-kirkwood/include/mach/gpio.h
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Expand Up @@ -6,33 +6,4 @@
* warranty of any kind, whether express or implied.
*/

#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H

#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */

#define GPIO_MAX 50
#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0140 : 0x0100)
#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00)
#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04)
#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08)
#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c)
#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10)
#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14)
#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18)
#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c)

static inline int gpio_to_irq(int pin)
{
return pin + IRQ_KIRKWOOD_GPIO_START;
}

static inline int irq_to_gpio(int irq)
{
return irq - IRQ_KIRKWOOD_GPIO_START;
}


#endif
2 changes: 2 additions & 0 deletions arch/arm/mach-kirkwood/include/mach/kirkwood.h
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Expand Up @@ -69,6 +69,8 @@
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140)
#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
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22 changes: 6 additions & 16 deletions arch/arm/mach-kirkwood/irq.c
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Expand Up @@ -27,31 +27,21 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)

void __init kirkwood_init_irq(void)
{
int i;

orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));

/*
* Mask and clear GPIO IRQ interrupts.
* Initialize gpiolib for GPIOs 0-49.
*/
writel(0, GPIO_LEVEL_MASK(0));
writel(0, GPIO_EDGE_MASK(0));
writel(0, GPIO_EDGE_CAUSE(0));
writel(0, GPIO_LEVEL_MASK(32));
writel(0, GPIO_EDGE_MASK(32));
writel(0, GPIO_EDGE_CAUSE(32));

for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);

orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START + 32);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
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3 changes: 0 additions & 3 deletions arch/arm/mach-kirkwood/mpp.c
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Expand Up @@ -49,9 +49,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
if (!variant_mask)
return;

/* Initialize gpiolib. */
orion_gpio_init();

printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));
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31 changes: 0 additions & 31 deletions arch/arm/mach-mv78xx0/include/mach/gpio.h
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Expand Up @@ -6,35 +6,4 @@
* warranty of any kind, whether express or implied.
*/

#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H

#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */

extern int mv78xx0_core_index(void);

#define GPIO_MAX 32
#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + 0x0100)
#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + 0x0104)
#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + 0x0108)
#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + 0x010c)
#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + 0x0110)
#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + 0x0114)
#define GPIO_MASK_OFF (mv78xx0_core_index() ? 0x18 : 0)
#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF)
#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF)

static inline int gpio_to_irq(int pin)
{
return pin + IRQ_MV78XX0_GPIO_START;
}

static inline int irq_to_gpio(int irq)
{
return irq - IRQ_MV78XX0_GPIO_START;
}


#endif
1 change: 1 addition & 0 deletions arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
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Expand Up @@ -71,6 +71,7 @@
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
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22 changes: 6 additions & 16 deletions arch/arm/mach-mv78xx0/irq.c
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Expand Up @@ -26,28 +26,18 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)

void __init mv78xx0_init_irq(void)
{
int i;

/* Initialize gpiolib. */
orion_gpio_init();

orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));

/*
* Mask and clear GPIO IRQ interrupts.
* Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
* registers for core #1 are at an offset of 0x18 from those of
* core #0.)
*/
writel(0, GPIO_LEVEL_MASK(0));
writel(0, GPIO_EDGE_MASK(0));
writel(0, GPIO_EDGE_CAUSE(0));

for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
orion_gpio_init(0, 32, GPIO_VIRT_BASE,
mv78xx0_core_index() ? 0x18 : 0,
IRQ_MV78XX0_GPIO_START);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
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3 changes: 0 additions & 3 deletions arch/arm/mach-mv78xx0/mpp.c
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Expand Up @@ -44,9 +44,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
if (!variant_mask)
return;

/* Initialize gpiolib. */
orion_gpio_init();

printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));
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28 changes: 0 additions & 28 deletions arch/arm/mach-orion5x/include/mach/gpio.h
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Expand Up @@ -6,32 +6,4 @@
* warranty of any kind, whether express or implied.
*/

#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H

#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */

#define GPIO_MAX 32
#define GPIO_OUT(pin) ORION5X_DEV_BUS_REG(0x100)
#define GPIO_IO_CONF(pin) ORION5X_DEV_BUS_REG(0x104)
#define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108)
#define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c)
#define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110)
#define GPIO_EDGE_CAUSE(pin) ORION5X_DEV_BUS_REG(0x114)
#define GPIO_EDGE_MASK(pin) ORION5X_DEV_BUS_REG(0x118)
#define GPIO_LEVEL_MASK(pin) ORION5X_DEV_BUS_REG(0x11c)

static inline int gpio_to_irq(int pin)
{
return pin + IRQ_ORION5X_GPIO_START;
}

static inline int irq_to_gpio(int irq)
{
return irq - IRQ_ORION5X_GPIO_START;
}


#endif
1 change: 1 addition & 0 deletions arch/arm/mach-orion5x/include/mach/orion5x.h
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Expand Up @@ -73,6 +73,7 @@
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
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19 changes: 2 additions & 17 deletions arch/arm/mach-orion5x/irq.c
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Expand Up @@ -28,27 +28,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)

void __init orion5x_init_irq(void)
{
int i;

orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);

/*
* Mask and clear GPIO IRQ interrupts
*/
writel(0x0, GPIO_LEVEL_MASK(0));
writel(0x0, GPIO_EDGE_MASK(0));
writel(0x0, GPIO_EDGE_CAUSE(0));

/*
* Register chained level handlers for GPIO IRQs by default.
* User can use set_type() if he wants to use edge types handlers.
* Initialize gpiolib for GPIOs 0-31.
*/
for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
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3 changes: 0 additions & 3 deletions arch/arm/mach-orion5x/mpp.c
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Expand Up @@ -124,9 +124,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);

/* Initialize gpiolib. */
orion_gpio_init();

for ( ; mode->mpp >= 0; mode++) {
u32 *reg;
int num_type;
Expand Down
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