Bug 1726303 - Rename internal opcodes to reflect final spec naming. r…

…=lth Differential Revision: https://phabricator.services.mozilla.com/D129304
dothq · Oct 25, 2021 · 163562f · 163562f
1 parent af3a6b1
commit 163562f
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Showing 16 changed files with 667 additions and 667 deletions.
diff --git a/js/src/jit/MIR.cpp b/js/src/jit/MIR.cpp
@@ -4800,7 +4800,7 @@ MDefinition* MWasmTernarySimd128::foldsTo(TempAllocator& alloc) {
 }
 
 MDefinition* MWasmBinarySimd128::foldsTo(TempAllocator& alloc) {
-  if (simdOp() == wasm::SimdOp::V8x16Swizzle && rhs()->isWasmFloatConstant()) {
+  if (simdOp() == wasm::SimdOp::I8x16Swizzle && rhs()->isWasmFloatConstant()) {
     // Specialize swizzle(v, constant) as shuffle(mask, v, zero) to trigger all
     // our shuffle optimizations.  We don't report this rewriting as the report
     // will be overwritten by the subsequent shuffle analysis.

diff --git a/js/src/jit/arm64/CodeGenerator-arm64.cpp b/js/src/jit/arm64/CodeGenerator-arm64.cpp
@@ -3056,19 +3056,19 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) {
     case wasm::SimdOp::I8x16Add:
       masm.addInt8x16(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I8x16AddSaturateS:
+    case wasm::SimdOp::I8x16AddSatS:
       masm.addSatInt8x16(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I8x16AddSaturateU:
+    case wasm::SimdOp::I8x16AddSatU:
       masm.unsignedAddSatInt8x16(lhs, rhs, dest);
       break;
     case wasm::SimdOp::I8x16Sub:
       masm.subInt8x16(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I8x16SubSaturateS:
+    case wasm::SimdOp::I8x16SubSatS:
       masm.subSatInt8x16(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I8x16SubSaturateU:
+    case wasm::SimdOp::I8x16SubSatU:
       masm.unsignedSubSatInt8x16(lhs, rhs, dest);
       break;
     case wasm::SimdOp::I8x16MinS:
@@ -3086,19 +3086,19 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) {
     case wasm::SimdOp::I16x8Add:
       masm.addInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8AddSaturateS:
+    case wasm::SimdOp::I16x8AddSatS:
       masm.addSatInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8AddSaturateU:
+    case wasm::SimdOp::I16x8AddSatU:
       masm.unsignedAddSatInt16x8(lhs, rhs, dest);
       break;
     case wasm::SimdOp::I16x8Sub:
       masm.subInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8SubSaturateS:
+    case wasm::SimdOp::I16x8SubSatS:
       masm.subSatInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8SubSaturateU:
+    case wasm::SimdOp::I16x8SubSatU:
       masm.unsignedSubSatInt16x8(lhs, rhs, dest);
       break;
     case wasm::SimdOp::I16x8Mul:
@@ -3185,22 +3185,22 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) {
     case wasm::SimdOp::F64x2Max:
       masm.maxFloat64x2(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::V8x16Swizzle:
+    case wasm::SimdOp::I8x16Swizzle:
       masm.swizzleInt8x16(lhs, rhs, dest);
       break;
     case wasm::SimdOp::V8x16RelaxedSwizzle:
       masm.swizzleInt8x16Relaxed(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I8x16NarrowSI16x8:
+    case wasm::SimdOp::I8x16NarrowI16x8S:
       masm.narrowInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I8x16NarrowUI16x8:
+    case wasm::SimdOp::I8x16NarrowI16x8U:
       masm.unsignedNarrowInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8NarrowSI32x4:
+    case wasm::SimdOp::I16x8NarrowI32x4S:
       masm.narrowInt32x4(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8NarrowUI32x4:
+    case wasm::SimdOp::I16x8NarrowI32x4U:
       masm.unsignedNarrowInt32x4(lhs, rhs, dest);
       break;
     case wasm::SimdOp::I8x16Eq:
@@ -3359,43 +3359,43 @@ void CodeGenerator::visitWasmBinarySimd128(LWasmBinarySimd128* ins) {
     case wasm::SimdOp::F64x2PMin:
       masm.pseudoMinFloat64x2(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I32x4DotSI16x8:
+    case wasm::SimdOp::I32x4DotI16x8S:
       masm.widenDotInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8ExtMulLowSI8x16:
+    case wasm::SimdOp::I16x8ExtmulLowI8x16S:
       masm.extMulLowInt8x16(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8ExtMulHighSI8x16:
+    case wasm::SimdOp::I16x8ExtmulHighI8x16S:
       masm.extMulHighInt8x16(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8ExtMulLowUI8x16:
+    case wasm::SimdOp::I16x8ExtmulLowI8x16U:
       masm.unsignedExtMulLowInt8x16(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I16x8ExtMulHighUI8x16:
+    case wasm::SimdOp::I16x8ExtmulHighI8x16U:
       masm.unsignedExtMulHighInt8x16(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I32x4ExtMulLowSI16x8:
+    case wasm::SimdOp::I32x4ExtmulLowI16x8S:
       masm.extMulLowInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I32x4ExtMulHighSI16x8:
+    case wasm::SimdOp::I32x4ExtmulHighI16x8S:
       masm.extMulHighInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I32x4ExtMulLowUI16x8:
+    case wasm::SimdOp::I32x4ExtmulLowI16x8U:
       masm.unsignedExtMulLowInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I32x4ExtMulHighUI16x8:
+    case wasm::SimdOp::I32x4ExtmulHighI16x8U:
       masm.unsignedExtMulHighInt16x8(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I64x2ExtMulLowSI32x4:
+    case wasm::SimdOp::I64x2ExtmulLowI32x4S:
       masm.extMulLowInt32x4(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I64x2ExtMulHighSI32x4:
+    case wasm::SimdOp::I64x2ExtmulHighI32x4S:
       masm.extMulHighInt32x4(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I64x2ExtMulLowUI32x4:
+    case wasm::SimdOp::I64x2ExtmulLowI32x4U:
       masm.unsignedExtMulLowInt32x4(lhs, rhs, dest);
       break;
-    case wasm::SimdOp::I64x2ExtMulHighUI32x4:
+    case wasm::SimdOp::I64x2ExtmulHighI32x4U:
       masm.unsignedExtMulHighInt32x4(lhs, rhs, dest);
       break;
     case wasm::SimdOp::I16x8Q15MulrSatS:
@@ -3783,27 +3783,27 @@ void CodeGenerator::visitWasmInt64ToSimd128(LWasmInt64ToSimd128* ins) {
     case wasm::SimdOp::I64x2Splat:
       masm.splatX2(src, dest);
       break;
-    case wasm::SimdOp::I16x8LoadS8x8:
+    case wasm::SimdOp::V128Load8x8S:
       masm.moveGPR64ToDouble(src, dest);
       masm.widenLowInt8x16(dest, dest);
       break;
-    case wasm::SimdOp::I16x8LoadU8x8:
+    case wasm::SimdOp::V128Load8x8U:
       masm.moveGPR64ToDouble(src, dest);
       masm.unsignedWidenLowInt8x16(dest, dest);
       break;
-    case wasm::SimdOp::I32x4LoadS16x4:
+    case wasm::SimdOp::V128Load16x4S:
       masm.moveGPR64ToDouble(src, dest);
       masm.widenLowInt16x8(dest, dest);
       break;
-    case wasm::SimdOp::I32x4LoadU16x4:
+    case wasm::SimdOp::V128Load16x4U:
       masm.moveGPR64ToDouble(src, dest);
       masm.unsignedWidenLowInt16x8(dest, dest);
       break;
-    case wasm::SimdOp::I64x2LoadS32x2:
+    case wasm::SimdOp::V128Load32x2S:
       masm.moveGPR64ToDouble(src, dest);
       masm.widenLowInt32x4(dest, dest);
       break;
-    case wasm::SimdOp::I64x2LoadU32x2:
+    case wasm::SimdOp::V128Load32x2U:
       masm.moveGPR64ToDouble(src, dest);
       masm.unsignedWidenLowInt32x4(dest, dest);
       break;
@@ -3827,52 +3827,52 @@ void CodeGenerator::visitWasmUnarySimd128(LWasmUnarySimd128* ins) {
     case wasm::SimdOp::I16x8Neg:
       masm.negInt16x8(src, dest);
       break;
-    case wasm::SimdOp::I16x8WidenLowSI8x16:
+    case wasm::SimdOp::I16x8ExtendLowI8x16S:
       masm.widenLowInt8x16(src, dest);
       break;
-    case wasm::SimdOp::I16x8WidenHighSI8x16:
+    case wasm::SimdOp::I16x8ExtendHighI8x16S:
       masm.widenHighInt8x16(src, dest);
       break;
-    case wasm::SimdOp::I16x8WidenLowUI8x16:
+    case wasm::SimdOp::I16x8ExtendLowI8x16U:
       masm.unsignedWidenLowInt8x16(src, dest);
       break;
-    case wasm::SimdOp::I16x8WidenHighUI8x16:
+    case wasm::SimdOp::I16x8ExtendHighI8x16U:
       masm.unsignedWidenHighInt8x16(src, dest);
       break;
     case wasm::SimdOp::I32x4Neg:
       masm.negInt32x4(src, dest);
       break;
-    case wasm::SimdOp::I32x4WidenLowSI16x8:
+    case wasm::SimdOp::I32x4ExtendLowI16x8S:
       masm.widenLowInt16x8(src, dest);
       break;
-    case wasm::SimdOp::I32x4WidenHighSI16x8:
+    case wasm::SimdOp::I32x4ExtendHighI16x8S:
       masm.widenHighInt16x8(src, dest);
       break;
-    case wasm::SimdOp::I32x4WidenLowUI16x8:
+    case wasm::SimdOp::I32x4ExtendLowI16x8U:
       masm.unsignedWidenLowInt16x8(src, dest);
       break;
-    case wasm::SimdOp::I32x4WidenHighUI16x8:
+    case wasm::SimdOp::I32x4ExtendHighI16x8U:
       masm.unsignedWidenHighInt16x8(src, dest);
       break;
-    case wasm::SimdOp::I32x4TruncSSatF32x4:
+    case wasm::SimdOp::I32x4TruncSatF32x4S:
       masm.truncSatFloat32x4ToInt32x4(src, dest);
       break;
-    case wasm::SimdOp::I32x4TruncUSatF32x4:
+    case wasm::SimdOp::I32x4TruncSatF32x4U:
       masm.unsignedTruncSatFloat32x4ToInt32x4(src, dest);
       break;
     case wasm::SimdOp::I64x2Neg:
       masm.negInt64x2(src, dest);
       break;
-    case wasm::SimdOp::I64x2WidenLowSI32x4:
+    case wasm::SimdOp::I64x2ExtendLowI32x4S:
       masm.widenLowInt32x4(src, dest);
       break;
-    case wasm::SimdOp::I64x2WidenHighSI32x4:
+    case wasm::SimdOp::I64x2ExtendHighI32x4S:
       masm.widenHighInt32x4(src, dest);
       break;
-    case wasm::SimdOp::I64x2WidenLowUI32x4:
+    case wasm::SimdOp::I64x2ExtendLowI32x4U:
       masm.unsignedWidenLowInt32x4(src, dest);
       break;
-    case wasm::SimdOp::I64x2WidenHighUI32x4:
+    case wasm::SimdOp::I64x2ExtendHighI32x4U:
       masm.unsignedWidenHighInt32x4(src, dest);
       break;
     case wasm::SimdOp::F32x4Abs:
@@ -3884,10 +3884,10 @@ void CodeGenerator::visitWasmUnarySimd128(LWasmUnarySimd128* ins) {
     case wasm::SimdOp::F32x4Sqrt:
       masm.sqrtFloat32x4(src, dest);
       break;
-    case wasm::SimdOp::F32x4ConvertSI32x4:
+    case wasm::SimdOp::F32x4ConvertI32x4S:
       masm.convertInt32x4ToFloat32x4(src, dest);
       break;
-    case wasm::SimdOp::F32x4ConvertUI32x4:
+    case wasm::SimdOp::F32x4ConvertI32x4U:
       masm.unsignedConvertInt32x4ToFloat32x4(src, dest);
       break;
     case wasm::SimdOp::F64x2Abs:
@@ -3957,16 +3957,16 @@ void CodeGenerator::visitWasmUnarySimd128(LWasmUnarySimd128* ins) {
       masm.unsignedTruncSatFloat64x2ToInt32x4(src, dest,
                                               ToFloatRegister(ins->temp()));
       break;
-    case wasm::SimdOp::I16x8ExtAddPairwiseI8x16S:
+    case wasm::SimdOp::I16x8ExtaddPairwiseI8x16S:
       masm.extAddPairwiseInt8x16(src, dest);
       break;
-    case wasm::SimdOp::I16x8ExtAddPairwiseI8x16U:
+    case wasm::SimdOp::I16x8ExtaddPairwiseI8x16U:
       masm.unsignedExtAddPairwiseInt8x16(src, dest);
       break;
-    case wasm::SimdOp::I32x4ExtAddPairwiseI16x8S:
+    case wasm::SimdOp::I32x4ExtaddPairwiseI16x8S:
       masm.extAddPairwiseInt16x8(src, dest);
       break;
-    case wasm::SimdOp::I32x4ExtAddPairwiseI16x8U:
+    case wasm::SimdOp::I32x4ExtaddPairwiseI16x8U:
       masm.unsignedExtAddPairwiseInt16x8(src, dest);
       break;
     case wasm::SimdOp::I8x16Popcnt:

diff --git a/js/src/jit/arm64/Lowering-arm64.cpp b/js/src/jit/arm64/Lowering-arm64.cpp
@@ -1269,22 +1269,22 @@ void LIRGenerator::visitWasmUnarySimd128(MWasmUnarySimd128* ins) {
     case wasm::SimdOp::I16x8Abs:
     case wasm::SimdOp::I32x4Abs:
     case wasm::SimdOp::I64x2Abs:
-    case wasm::SimdOp::I32x4TruncSSatF32x4:
-    case wasm::SimdOp::F32x4ConvertUI32x4:
-    case wasm::SimdOp::I32x4TruncUSatF32x4:
-    case wasm::SimdOp::I16x8WidenLowSI8x16:
-    case wasm::SimdOp::I16x8WidenHighSI8x16:
-    case wasm::SimdOp::I16x8WidenLowUI8x16:
-    case wasm::SimdOp::I16x8WidenHighUI8x16:
-    case wasm::SimdOp::I32x4WidenLowSI16x8:
-    case wasm::SimdOp::I32x4WidenHighSI16x8:
-    case wasm::SimdOp::I32x4WidenLowUI16x8:
-    case wasm::SimdOp::I32x4WidenHighUI16x8:
-    case wasm::SimdOp::I64x2WidenLowSI32x4:
-    case wasm::SimdOp::I64x2WidenHighSI32x4:
-    case wasm::SimdOp::I64x2WidenLowUI32x4:
-    case wasm::SimdOp::I64x2WidenHighUI32x4:
-    case wasm::SimdOp::F32x4ConvertSI32x4:
+    case wasm::SimdOp::I32x4TruncSatF32x4S:
+    case wasm::SimdOp::F32x4ConvertI32x4U:
+    case wasm::SimdOp::I32x4TruncSatF32x4U:
+    case wasm::SimdOp::I16x8ExtendLowI8x16S:
+    case wasm::SimdOp::I16x8ExtendHighI8x16S:
+    case wasm::SimdOp::I16x8ExtendLowI8x16U:
+    case wasm::SimdOp::I16x8ExtendHighI8x16U:
+    case wasm::SimdOp::I32x4ExtendLowI16x8S:
+    case wasm::SimdOp::I32x4ExtendHighI16x8S:
+    case wasm::SimdOp::I32x4ExtendLowI16x8U:
+    case wasm::SimdOp::I32x4ExtendHighI16x8U:
+    case wasm::SimdOp::I64x2ExtendLowI32x4S:
+    case wasm::SimdOp::I64x2ExtendHighI32x4S:
+    case wasm::SimdOp::I64x2ExtendLowI32x4U:
+    case wasm::SimdOp::I64x2ExtendHighI32x4U:
+    case wasm::SimdOp::F32x4ConvertI32x4S:
     case wasm::SimdOp::F32x4Ceil:
     case wasm::SimdOp::F32x4Floor:
     case wasm::SimdOp::F32x4Trunc:
@@ -1297,10 +1297,10 @@ void LIRGenerator::visitWasmUnarySimd128(MWasmUnarySimd128* ins) {
     case wasm::SimdOp::F64x2PromoteLowF32x4:
     case wasm::SimdOp::F64x2ConvertLowI32x4S:
     case wasm::SimdOp::F64x2ConvertLowI32x4U:
-    case wasm::SimdOp::I16x8ExtAddPairwiseI8x16S:
-    case wasm::SimdOp::I16x8ExtAddPairwiseI8x16U:
-    case wasm::SimdOp::I32x4ExtAddPairwiseI16x8S:
-    case wasm::SimdOp::I32x4ExtAddPairwiseI16x8U:
+    case wasm::SimdOp::I16x8ExtaddPairwiseI8x16S:
+    case wasm::SimdOp::I16x8ExtaddPairwiseI8x16U:
+    case wasm::SimdOp::I32x4ExtaddPairwiseI16x8S:
+    case wasm::SimdOp::I32x4ExtaddPairwiseI16x8U:
     case wasm::SimdOp::I8x16Popcnt:
     case wasm::SimdOp::I32x4RelaxedTruncSSatF32x4:
     case wasm::SimdOp::I32x4RelaxedTruncUSatF32x4:

diff --git a/js/src/jit/arm64/MacroAssembler-arm64.cpp b/js/src/jit/arm64/MacroAssembler-arm64.cpp
@@ -493,22 +493,22 @@ void MacroAssemblerCompat::wasmLoadImpl(const wasm::MemoryAccessDesc& access,
           } else {
             MOZ_ASSERT(access.isWidenSimd128Load());
             switch (access.widenSimdOp()) {
-              case wasm::SimdOp::I16x8LoadS8x8:
+              case wasm::SimdOp::V128Load8x8S:
                 Sshll(SelectFPReg(outany, out64, 128).V8H(), scratch.V8B(), 0);
                 break;
-              case wasm::SimdOp::I16x8LoadU8x8:
+              case wasm::SimdOp::V128Load8x8U:
                 Ushll(SelectFPReg(outany, out64, 128).V8H(), scratch.V8B(), 0);
                 break;
-              case wasm::SimdOp::I32x4LoadS16x4:
+              case wasm::SimdOp::V128Load16x4S:
                 Sshll(SelectFPReg(outany, out64, 128).V4S(), scratch.V4H(), 0);
                 break;
-              case wasm::SimdOp::I32x4LoadU16x4:
+              case wasm::SimdOp::V128Load16x4U:
                 Ushll(SelectFPReg(outany, out64, 128).V4S(), scratch.V4H(), 0);
                 break;
-              case wasm::SimdOp::I64x2LoadS32x2:
+              case wasm::SimdOp::V128Load32x2S:
                 Sshll(SelectFPReg(outany, out64, 128).V2D(), scratch.V2S(), 0);
                 break;
-              case wasm::SimdOp::I64x2LoadU32x2:
+              case wasm::SimdOp::V128Load32x2U:
                 Ushll(SelectFPReg(outany, out64, 128).V2D(), scratch.V2S(), 0);
                 break;
               default:

diff --git a/js/src/jit/x64/MacroAssembler-x64.cpp b/js/src/jit/x64/MacroAssembler-x64.cpp
@@ -957,22 +957,22 @@ void MacroAssembler::wasmLoad(const wasm::MemoryAccessDesc& access,
         vmovddup(srcAddr, out.fpu());
       } else if (access.isWidenSimd128Load()) {
         switch (access.widenSimdOp()) {
-          case wasm::SimdOp::I16x8LoadS8x8:
+          case wasm::SimdOp::V128Load8x8S:
             vpmovsxbw(srcAddr, out.fpu());
             break;
-          case wasm::SimdOp::I16x8LoadU8x8:
+          case wasm::SimdOp::V128Load8x8U:
             vpmovzxbw(srcAddr, out.fpu());
             break;
-          case wasm::SimdOp::I32x4LoadS16x4:
+          case wasm::SimdOp::V128Load16x4S:
             vpmovsxwd(srcAddr, out.fpu());
             break;
-          case wasm::SimdOp::I32x4LoadU16x4:
+          case wasm::SimdOp::V128Load16x4U:
             vpmovzxwd(srcAddr, out.fpu());
             break;
-          case wasm::SimdOp::I64x2LoadS32x2:
+          case wasm::SimdOp::V128Load32x2S:
             vpmovsxdq(srcAddr, out.fpu());
             break;
-          case wasm::SimdOp::I64x2LoadU32x2:
+          case wasm::SimdOp::V128Load32x2U:
             vpmovzxdq(srcAddr, out.fpu());
             break;
           default: