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Commits on Jul 28, 2023

• VEX IR generator added for RISCV WFI instruction

  EvelynVusky

  committed
  24a85ec

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Commits on May 13, 2023

• Add Build workflow (angr#55)

  Show description for 7fec1bc
  

  twizmwazin

  authored and

  rhelmot

  committed
  7fec1bc

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• add ctzll shim for msvc

  rhelmot

  committed
  b96e9ff

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• MSVC compat for risc-v

  rhelmot

  committed
  2d26e0e

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• riscv: add floating point registers to genoffsets

  

  alikates

  authored and

  rhelmot

  committed
  a1b3085

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• riscv: fix instructions that use the unsupported Ity_1 data type

  

  alikates

  authored and

  rhelmot

  committed
  7576d04

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• add guest__use_fallback_LLSC field to VexAbiInfo because RISC-V code uses it

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  alikates

  authored and

  rhelmot

  committed
  950ab4a

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• add RISC-V to supported list in ir_opt

  

  alikates

  authored and

  rhelmot

  committed
  fd65310

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• riscv: fix vassert symbol not found by reordering/adding some includes

  

  alikates

  authored and

  rhelmot

  committed
  b2f5d64

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• riscv: remove unsupported Iops

  

  alikates

  authored and

  rhelmot

  committed
  7c43969

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• fix disInstr_RISCV64 function signature

  

  alikates

  authored and

  rhelmot

  committed
  5e8d1c4

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• Add RISCV64 support

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  petrpavlu

  authored and

  rhelmot

  committed
  02ae513

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Commits on Jan 12, 2023

• Implement fnop; closes angr/pyvex#290

  rhelmot

  committed
  e75200b

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Commits on Dec 1, 2022

• Feat/amd64 retf (angr#53)

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  dannyp303

  and

  Dan Pesce

  authored
  e8a5589

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Commits on Oct 28, 2022

• Fix copy-paste issue in question template

  zwimer

  authored
  f19e2f5

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• Fix copy-paste issue in feature request template

  zwimer

  authored
  f409cc9

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• Fix copy-paste issue in bug report template

  zwimer

  authored
  a973cb7

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Commits on Oct 26, 2022

• Update issue management

  twizmwazin

  committed
  8c91915

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Commits on Oct 12, 2022

• amd64: support read/write segment registers as if they were general-purpose (angr#51)

  rhelmot

  authored
  064b3fd

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Commits on Jul 5, 2022

• AMD64: Support rdsspd/rdsspq. (angr#49)

  ltfish

  authored
  6ec2c3f

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Commits on Apr 8, 2022

• Remove VERSION file

  twizmwazin

  committed
  0e19d11

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Commits on Mar 16, 2022

• Truncate ADDL args to 32bit

  rhelmot

  committed
  5e416aa

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Commits on Dec 23, 2021

• AMD64: Add a spechelper for ADDL and CondZ. (angr#47)

  ltfish

  authored
  9bcfa42

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Commits on Dec 17, 2021

• ARM: Add spechelpers for ADD-EQ/NE. (angr#45)

  ltfish

  authored
  5b3cab1

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• ARM: Support sub.w reg, reg, reg, lsl #0-4. (angr#46)

  ltfish

  authored
  375924d

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Commits on Dec 13, 2021

• Bump minor version to 9.1

  rhelmot

  committed
  bcd63c8

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Commits on Sep 21, 2021

• Opt: Do not disable optimizations of VEX-specific registers. (angr#44)

  ltfish

  authored
  3440a56

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Commits on Sep 18, 2021

• Support lifting ARM syscalls under OABI. (angr#43)

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  degrigis

  and

  rhelmot

  authored
  a6576a1

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Commits on Aug 19, 2021

• Don't truncate 64-bit segment base in 32-bit addressing mode. (angr#42)

  edmcman

  authored
  85259cb

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Commits on Jun 20, 2021

• Provide explicit amount of lookback information to vex (angr#40)

  rhelmot

  authored
  0feb7ff

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Commits on May 20, 2021

• Fix ldrsw rX, [literal]; closes angr/pyvex#222

  rhelmot

  committed
  dfb44e7

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Commits on Apr 29, 2021

• Add flag to disable handling valgrind-special NOPs

  rhelmot

  committed
  efdd6c3

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Commits on Oct 1, 2020

• Add VERSION file

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  twizmwazin

  committed
  939f423

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Commits on Jul 18, 2020

• [WIP] amd64_toIR: Decode endbr. (angr#38)

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  ltfish

  and

  rhelmot

  authored
  4648030

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Commits on May 30, 2020

• Add support for GCC 10

  

  Harry

  authored and

  rhelmot

  committed
  4b15a93

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