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ltfish

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Commits on Jul 5, 2022

• AMD64: Support rdsspd/rdsspq. (angr#49)

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Commits on Dec 23, 2021

• AMD64: Add a spechelper for ADDL and CondZ. (angr#47)

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Commits on Dec 17, 2021

• ARM: Add spechelpers for ADD-EQ/NE. (angr#45)

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  5b3cab1

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• ARM: Support sub.w reg, reg, reg, lsl #0-4. (angr#46)

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Commits on Sep 21, 2021

• Opt: Do not disable optimizations of VEX-specific registers. (angr#44)

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Commits on Jul 18, 2020

• [WIP] amd64_toIR: Decode endbr. (angr#38)

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  4648030

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Commits on May 19, 2020

• Generate libvex_guest_offsets.h. Fix angr/pyvex#214.

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  f5b9c74

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Commits on May 4, 2020

• Opt: Support disabling cross-instruction optimizations. (angr#35)

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Commits on Feb 15, 2020

• Eliminate case x+1 ... x+N.

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  8747162

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• Eliminate empty structs.

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• Make FIND_OR_MAKE_FREE_RREG a code block instead of an expression.

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  fa3306e

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• Provide builtin replacements for clzll and ctzll.

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  91fbdd5

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• Convert an enum to defines so they can be used in switch-cases.

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  4d02587

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• s390_calculate_cc() should always return something.

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  4b2c141

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• long is 32-bit long in Win64.

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Commits on Jan 18, 2020

• ARM: Support decoding semihosting (svc 0x123456). (angr#30)

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  6955cf7

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Commits on Jan 7, 2020

• Implement strict_block_end for loop, jrcxz, jecxz on AMD64. (angr#29)

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Commits on Mar 3, 2019

• Merge pull request angr#24 from angr/fix/arm_ldmfd_sp_pc_ret

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Commits on Mar 2, 2019

• ARM: Mark LDMFD SP, {xxx, SP, PC} as a return instruction.

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Commits on Jul 5, 2018

• ARM: Mark LDMDB R11, {xxx, pc} as a return instruction. (angr#16)

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Commits on Jun 30, 2017

• Mkae sure HWord is 64-bit on Win64.

  

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  c49ae25

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Commits on Mar 16, 2017

• mips_toir: change opcode for jal from 0x2 to 0x3

  

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  rhelmot

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  ba338fe

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• mips_toIR: Make exits created by 'jr $ra' have jumpkind=Ijk_Ret

  

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  775e668

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• arm_toIR: Add support for instruction "svc number" where number is greater than 0

  

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