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target/mips: introduce decodetree structure for Cavium Octeon extension
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This patch adds decodetree for Cavium Octeon extension and
an instruction set extension flag for using it in CPU models.

Signed-off-by: Pavel Dovgalyuk <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
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Dovgalyuk authored and philmd committed Jul 12, 2022
1 parent 8e3d85d commit 72d680e
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Showing 6 changed files with 31 additions and 0 deletions.
1 change: 1 addition & 0 deletions target/mips/mips-defs.h
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@
#define INSN_LOONGSON2E 0x0000040000000000ULL
#define INSN_LOONGSON2F 0x0000080000000000ULL
#define INSN_LOONGSON3A 0x0000100000000000ULL
#define INSN_OCTEON 0x0000200000000000ULL
/*
* bits 52-63: vendor-specific ASEs
*/
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2 changes: 2 additions & 0 deletions target/mips/tcg/meson.build
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Expand Up @@ -3,6 +3,7 @@ gen = [
decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'),
decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'),
]

mips_ss.add(gen)
Expand All @@ -24,6 +25,7 @@ mips_ss.add(files(
))
mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
'tx79_translate.c',
'octeon_translate.c',
), if_false: files(
'mxu_translate.c',
))
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6 changes: 6 additions & 0 deletions target/mips/tcg/octeon.decode
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@@ -0,0 +1,6 @@
# Octeon Architecture Module instruction set
#
# Copyright (C) 2022 Pavel Dovgalyuk
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
16 changes: 16 additions & 0 deletions target/mips/tcg/octeon_translate.c
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@@ -0,0 +1,16 @@
/*
* Octeon-specific instructions translation routines
*
* Copyright (c) 2022 Pavel Dovgalyuk
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/

#include "qemu/osdep.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
#include "exec/helper-gen.h"
#include "translate.h"

/* Include the auto-generated decoder. */
#include "decode-octeon.c.inc"
5 changes: 5 additions & 0 deletions target/mips/tcg/translate.c
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Expand Up @@ -15955,6 +15955,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
return;
}
#if defined(TARGET_MIPS64)
if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) {
return;
}
#endif

/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
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1 change: 1 addition & 0 deletions target/mips/tcg/translate.h
Original file line number Diff line number Diff line change
Expand Up @@ -215,6 +215,7 @@ bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
bool decode_ext_octeon(DisasContext *ctx, uint32_t insn);
#endif
bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);

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