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cpu: Remove CPU_COMMON
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This macro is now always empty, so remove it.  This leaves the
entire contents of CPUArchState under the control of the guest
architecture.

Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
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rth7680 committed Jun 10, 2019
1 parent 269bd5d commit e8b5fae
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Showing 22 changed files with 2 additions and 50 deletions.
2 changes: 0 additions & 2 deletions include/exec/cpu-defs.h
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Expand Up @@ -231,8 +231,6 @@ typedef struct CPUTLB { } CPUTLB;

#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */

#define CPU_COMMON /* Nothing */

/*
* This structure must be placed in ArchCPU immedately
* before CPUArchState, as a field named "neg".
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3 changes: 0 additions & 3 deletions target/alpha/cpu.h
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Expand Up @@ -251,9 +251,6 @@ struct CPUAlphaState {
/* This alarm doesn't exist in real hardware; we wish it did. */
uint64_t alarm_expire;

/* Those resources are used only in QEMU core */
CPU_COMMON

int error_code;

uint32_t features;
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4 changes: 1 addition & 3 deletions target/arm/cpu.h
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Expand Up @@ -645,9 +645,7 @@ typedef struct CPUARMState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Fields after CPU_COMMON are preserved across CPU reset. */
/* Fields after this point are preserved across CPU reset. */

/* Internal CPU feature flags. */
uint64_t features;
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2 changes: 0 additions & 2 deletions target/cris/cpu.h
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Expand Up @@ -163,8 +163,6 @@ typedef struct CPUCRISState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Members from load_info on are preserved across resets. */
void *load_info;
} CPUCRISState;
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3 changes: 0 additions & 3 deletions target/hppa/cpu.h
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Expand Up @@ -197,9 +197,6 @@ struct CPUHPPAState {
target_ureg cr_back[2]; /* back of cr17/cr18 */
target_ureg shadow[7]; /* shadow registers */

/* Those resources are used only in QEMU core */
CPU_COMMON

/* ??? The number of entries isn't specified by the architecture. */
/* ??? Implement a unified itlb/dtlb for the moment. */
/* ??? We should use a more intelligent data structure. */
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4 changes: 1 addition & 3 deletions target/i386/cpu.h
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Expand Up @@ -1289,9 +1289,7 @@ typedef struct CPUX86State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Fields after CPU_COMMON are preserved across CPU reset. */
/* Fields after this point are preserved across CPU reset. */

/* processor features (e.g. for CPUID insn) */
/* Minimum level/xlevel/xlevel2, based on CPU model + features */
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2 changes: 0 additions & 2 deletions target/lm32/cpu.h
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Expand Up @@ -159,8 +159,6 @@ struct CPULM32State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Fields from here on are preserved across CPU reset. */
uint32_t eba; /* exception base address */
uint32_t deba; /* debug exception base address */
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2 changes: 0 additions & 2 deletions target/m68k/cpu.h
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Expand Up @@ -143,8 +143,6 @@ typedef struct CPUM68KState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Fields from here on are preserved across CPU reset. */
uint32_t features;
} CPUM68KState;
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2 changes: 0 additions & 2 deletions target/microblaze/cpu.h
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Expand Up @@ -266,8 +266,6 @@ struct CPUMBState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* These fields are preserved on reset. */

struct {
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2 changes: 0 additions & 2 deletions target/mips/cpu.h
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Expand Up @@ -1041,8 +1041,6 @@ struct CPUMIPSState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Fields from here on are preserved across CPU reset. */
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
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3 changes: 0 additions & 3 deletions target/moxie/cpu.h
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Expand Up @@ -45,9 +45,6 @@ typedef struct CPUMoxieState {

/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

} CPUMoxieState;

#include "qom/cpu.h"
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2 changes: 0 additions & 2 deletions target/nios2/cpu.h
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Expand Up @@ -167,8 +167,6 @@ struct CPUNios2State {

uint32_t irq_pending;
#endif

CPU_COMMON
};

/**
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2 changes: 0 additions & 2 deletions target/openrisc/cpu.h
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Expand Up @@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Fields from here on are preserved across CPU reset. */
uint32_t cpucfgr; /* CPU configure register */

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2 changes: 0 additions & 2 deletions target/ppc/cpu.h
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Expand Up @@ -999,8 +999,6 @@ struct CPUPPCState {
/* when a memory exception occurs, the access type is stored here */
int access_type;

CPU_COMMON

/* MMU context - only relevant for full system emulation */
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
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3 changes: 0 additions & 3 deletions target/riscv/cpu.h
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Expand Up @@ -171,9 +171,6 @@ struct CPURISCVState {

float_status fp_status;

/* QEMU */
CPU_COMMON

/* Fields from here on are preserved across CPU reset. */
QEMUTimer *timer; /* Internal timer */
};
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2 changes: 0 additions & 2 deletions target/s390x/cpu.h
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Expand Up @@ -114,8 +114,6 @@ struct CPUS390XState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

#if !defined(CONFIG_USER_ONLY)
uint32_t core_id; /* PoP "CPU address", same as cpu_index */
uint64_t cpuid;
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2 changes: 0 additions & 2 deletions target/sh4/cpu.h
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Expand Up @@ -179,8 +179,6 @@ typedef struct CPUSH4State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Fields from here on are preserved over CPU reset. */
int id; /* CPU model */

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2 changes: 0 additions & 2 deletions target/sparc/cpu.h
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Expand Up @@ -446,8 +446,6 @@ struct CPUSPARCState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON

/* Fields from here on are preserved across CPU reset. */
target_ulong version;
uint32_t nwindows;
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2 changes: 0 additions & 2 deletions target/tilegx/cpu.h
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Expand Up @@ -93,8 +93,6 @@ typedef struct CPUTLGState {

/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

CPU_COMMON
} CPUTLGState;

#include "qom/cpu.h"
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2 changes: 0 additions & 2 deletions target/tricore/cpu.h
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Expand Up @@ -184,8 +184,6 @@ struct CPUTriCoreState {
int error_code;
uint32_t hflags; /* CPU State */

CPU_COMMON

/* Internal CPU feature flags. */
uint64_t features;

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2 changes: 0 additions & 2 deletions target/unicore32/cpu.h
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Expand Up @@ -55,8 +55,6 @@ typedef struct CPUUniCore32State {
float_status fp_status;
} ucf64;

CPU_COMMON

/* Internal CPU feature flags. */
uint32_t features;

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2 changes: 0 additions & 2 deletions target/xtensa/cpu.h
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Expand Up @@ -541,8 +541,6 @@ typedef struct CPUXtensaState {

/* Watchpoints for DBREAK registers */
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];

CPU_COMMON
} CPUXtensaState;

/**
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