Verilator open-source SystemVerilog simulator and lint system

Generator of random circuits

A modern hardware definition language and toolchain based on Python

A Hardware Description Language

An experimental hardware compiler

high-performance RTL simulator

Simple RISC-V 3-stage Pipeline in Chisel

Using e-graphs to synthesize netlists from boolean logic.

Test suite designed to check compliance with the SystemVerilog standard.

Reusable GitHub Action Workflow to update CIRCT in a downstream project

an experiment to run plugin in firtool pipeline

SystemVerilog compiler and language services

An SMT dialect for MLIR, to represent SMTLib programs. And tools to interact with SMT solvers.

Flexible Intermediate Representation for RTL

Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older versio…

CIRCT website

A Just-In-Time Compiler for Verilog from VMware Research

Circuit IR Compilers and Tools

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

Demonstration of a project using sifive/chisel-circt

Vim syntax highlight for Chisel