GlobalISel: remove "unsized" LLT

It was only really there as a sentinel when instructions had to have precisely
one type. Now that registers are typed, each register really has to have a type
that is sized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281599 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/LowLevelType.h

@@ -14,7 +14,6 @@
 /// size and the number of vector lanes (if any). Accordingly, there are 4
 /// possible valid type-kinds:
 ///
-///    * `unsized` for labels etc
 ///    * `sN` for scalars and aggregates
 ///    * `<N x sM>` for vectors, which must have at least 2 elements.
 ///    * `pN` for pointers
@@ -46,7 +45,6 @@ class LLT {
     Scalar,
     Pointer,
     Vector,
-    Unsized,
   };
 
   /// Get a low-level scalar or aggregate "bag of bits".
@@ -74,11 +72,6 @@ class LLT {
     return LLT{Vector, NumElements, ScalarTy.getSizeInBits()};
   }
 
-  /// Get an unsized but valid low-level type (e.g. for a label).
-  static LLT unsized() {
-    return LLT{Unsized, 0, 0};
-  }
-
   explicit LLT(TypeKind Kind, uint16_t NumElements, unsigned SizeInBits)
     : SizeInBits(SizeInBits), ElementsOrAddrSpace(NumElements), Kind(Kind) {
     assert((Kind != Vector || ElementsOrAddrSpace > 1) &&
@@ -98,10 +91,6 @@ class LLT {
 
   bool isVector() const { return Kind == Vector; }
 
-  bool isSized() const {
-    return Kind == Scalar || Kind == Vector || Kind == Pointer;
-  }
-
   /// Returns the number of elements in a vector LLT. Must only be called on
   /// vector types.
   uint16_t getNumElements() const {
@@ -111,14 +100,12 @@ class LLT {
 
   /// Returns the total size of the type. Must only be called on sized types.
   unsigned getSizeInBits() const {
-    assert(isSized() && "attempt to get size of unsized type");
     if (isPointer() || isScalar())
       return SizeInBits;
     return SizeInBits * ElementsOrAddrSpace;
   }
 
   unsigned getScalarSizeInBits() const {
-    assert(isSized() && "cannot get size of this type");
     return SizeInBits;
   }
 
@@ -137,7 +124,7 @@ class LLT {
   /// size of the scalar type involved. For example `s32` will become `s16`,
   /// `<2 x s32>` will become `<2 x s16>`.
   LLT halfScalarSize() const {
-    assert(isSized() && getScalarSizeInBits() > 1 &&
+    assert(!isPointer() && getScalarSizeInBits() > 1 &&
            getScalarSizeInBits() % 2 == 0 && "cannot half size of this type");
     return LLT{Kind, ElementsOrAddrSpace, SizeInBits / 2};
   }
@@ -146,7 +133,7 @@ class LLT {
   /// size of the scalar type involved. For example `s32` will become `s64`,
   /// `<2 x s32>` will become `<2 x s64>`.
   LLT doubleScalarSize() const {
-    assert(isSized() && "cannot change size of this type");
+    assert(!isPointer() && "cannot change size of this type");
     return LLT{Kind, ElementsOrAddrSpace, SizeInBits * 2};
   }
 
@@ -169,6 +156,7 @@ class LLT {
   /// a vector type. For example `<2 x s32>` will become `<4 x s32>`. Doubling
   /// the number of elements in sN produces <2 x sN>.
   LLT doubleElements() const {
+    assert(!isPointer() && "cannot double elements in pointer");
     return LLT{Vector, static_cast<uint16_t>(ElementsOrAddrSpace * 2),
                SizeInBits};
   }

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

@@ -367,7 +367,7 @@ unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
     RC = TRI.getMinimalPhysRegClass(Reg);
   } else {
     LLT Ty = MRI.getType(Reg);
-    unsigned RegSize = Ty.isSized() ? Ty.getSizeInBits() : 0;
+    unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
     // If Reg is not a generic register, query the register class to
     // get its size.
     if (RegSize)

lib/CodeGen/LowLevelType.cpp

@@ -35,7 +35,7 @@ LLT::LLT(Type &Ty, const DataLayout &DL) {
     ElementsOrAddrSpace = 1;
     assert(SizeInBits != 0 && "invalid zero-sized type");
   } else {
-    Kind = Unsized;
+    Kind = Invalid;
     SizeInBits = ElementsOrAddrSpace = 0;
   }
 }
@@ -45,10 +45,9 @@ void LLT::print(raw_ostream &OS) const {
     OS << "<" << ElementsOrAddrSpace << " x s" << SizeInBits << ">";
   else if (isPointer())
     OS << "p" << getAddressSpace();
-  else if (isSized())
+  else if (isValid()) {
+    assert(isScalar() && "unexpected type");
     OS << "s" << getScalarSizeInBits();
-  else if (isValid())
-    OS << "unsized";
-  else
+  } else
     llvm_unreachable("trying to print an invalid type");
 }

lib/CodeGen/MIRParser/MIParser.cpp

@@ -1039,11 +1039,7 @@ bool MIParser::parseIRConstant(StringRef::iterator Loc, const Constant *&C) {
 }
 
 bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
-  if (Token.is(MIToken::Identifier) && Token.stringValue() == "unsized") {
-    lex();
-    Ty = LLT::unsized();
-    return false;
-  } else if (Token.is(MIToken::ScalarType)) {
+  if (Token.is(MIToken::ScalarType)) {
     Ty = LLT::scalar(APSInt(Token.range().drop_front()).getZExtValue());
     lex();
     return false;

lib/CodeGen/MachineRegisterInfo.cpp

@@ -143,7 +143,7 @@ void MachineRegisterInfo::clearVirtRegTypes() {
   // Verify that the size of the now-constrained vreg is unchanged.
   for (auto &VRegToType : getVRegToType()) {
     auto *RC = getRegClass(VRegToType.first);
-    if (VRegToType.second.isSized() &&
+    if (VRegToType.second.isValid() &&
         VRegToType.second.getSizeInBits() > (RC->getSize() * 8))
       llvm_unreachable(
           "Virtual register has explicit size different from its class size");

lib/CodeGen/MachineVerifier.cpp

@@ -1051,7 +1051,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
           }
 
           // Make sure the register fits into its register bank if any.
-          if (RegBank && Ty.isSized() &&
+          if (RegBank && Ty.isValid() &&
               RegBank->getSize() < Ty.getSizeInBits()) {
             report("Register bank is too small for virtual register", MO,
                    MONum);

lib/Target/AArch64/AArch64InstructionSelector.cpp

@@ -50,8 +50,8 @@ static bool unsupportedBinOp(const MachineInstr &I,
                              const MachineRegisterInfo &MRI,
                              const AArch64RegisterInfo &TRI) {
   LLT Ty = MRI.getType(I.getOperand(0).getReg());
-  if (!Ty.isSized()) {
-    DEBUG(dbgs() << "Generic binop should be sized\n");
+  if (!Ty.isValid()) {
+    DEBUG(dbgs() << "Generic binop register should be typed\n");
     return true;
   }
 
@@ -220,9 +220,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     return false;
   }
 
-  const LLT Ty = I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg())
-                                         : LLT::unsized();
-  assert(Ty.isValid() && "Generic instruction doesn't have a type");
+  LLT Ty =
+      I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
 
   switch (I.getOpcode()) {
   case TargetOpcode::G_BR: {

lib/Target/AArch64/AArch64MachineLegalizer.cpp

@@ -149,7 +149,6 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
   }
 
   // Control-flow
-  setAction({G_BR, LLT::unsized()}, Legal);
   setAction({G_BRCOND, s32}, Legal);
   for (auto Ty : {s1, s8, s16})
     setAction({G_BRCOND, Ty}, WidenScalar);

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

@@ -188,7 +188,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     BankID = AArch64::GPRRegBankID;
 
   Mapping = InstructionMapping{1, 1, MI.getNumOperands()};
-  int Size = Ty.isSized() ? Ty.getSizeInBits() : 0;
+  int Size = Ty.isValid() ? Ty.getSizeInBits() : 0;
   for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
     Mapping.setOperandMapping(Idx, Size, getRegBank(BankID));
 

unittests/CodeGen/LowLevelTypeTest.cpp

@@ -43,7 +43,6 @@ TEST(LowLevelTypeTest, Scalar) {
     for (const LLT TestTy : {Ty, HalfTy, DoubleTy}) {
       ASSERT_TRUE(TestTy.isValid());
       ASSERT_TRUE(TestTy.isScalar());
-      ASSERT_TRUE(TestTy.isSized());
 
       ASSERT_FALSE(TestTy.isPointer());
       ASSERT_FALSE(TestTy.isVector());
@@ -101,7 +100,6 @@ TEST(LowLevelTypeTest, Vector) {
       // Test kind.
       for (const LLT TestTy : {VTy, HalfSzTy, DoubleSzTy, DoubleEltTy}) {
         ASSERT_TRUE(TestTy.isValid());
-        ASSERT_TRUE(TestTy.isSized());
         ASSERT_TRUE(TestTy.isVector());
 
         ASSERT_FALSE(TestTy.isScalar());
@@ -111,7 +109,6 @@ TEST(LowLevelTypeTest, Vector) {
       // Test halving elements to a scalar.
       {
         ASSERT_TRUE(HalfEltIfEvenTy.isValid());
-        ASSERT_TRUE(HalfEltIfEvenTy.isSized());
         ASSERT_FALSE(HalfEltIfEvenTy.isPointer());
         if (Elts > 2) {
           ASSERT_TRUE(HalfEltIfEvenTy.isVector());
@@ -178,7 +175,6 @@ TEST(LowLevelTypeTest, Pointer) {
     // Test kind.
     ASSERT_TRUE(Ty.isValid());
     ASSERT_TRUE(Ty.isPointer());
-    ASSERT_TRUE(Ty.isSized());
 
     ASSERT_FALSE(Ty.isScalar());
     ASSERT_FALSE(Ty.isVector());
@@ -201,24 +197,8 @@ TEST(LowLevelTypeTest, Invalid) {
 
   ASSERT_FALSE(Ty.isValid());
   ASSERT_FALSE(Ty.isScalar());
-  ASSERT_FALSE(Ty.isSized());
   ASSERT_FALSE(Ty.isPointer());
   ASSERT_FALSE(Ty.isVector());
 }
 
-TEST(LowLevelTypeTest, Unsized) {
-  LLVMContext C;
-  DataLayout DL("");
-
-  const LLT Ty = LLT::unsized();
-
-  ASSERT_TRUE(Ty.isValid());
-  ASSERT_FALSE(Ty.isScalar());
-  ASSERT_FALSE(Ty.isSized());
-  ASSERT_FALSE(Ty.isPointer());
-  ASSERT_FALSE(Ty.isVector());
-
-  Type *IRTy = Type::getLabelTy(C);
-  EXPECT_EQ(Ty, LLT(*IRTy, DL));
-}
 }