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[llvm-mca] add flag -all-views and flag -all-stats.
Flag -all-views enables all the views. Flag -all-stats enables all the views that print hardware statistics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332602 91177308-0d34-0410-b5e6-96231b3b80d8
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Andrea Di Biagio
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Andrea Di Biagio
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May 17, 2018
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULLREPORT | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats=true < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULLREPORT | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats=false < %s | FileCheck %s -check-prefix=ALL | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 < %s | FileCheck %s -check-prefix=ALL | ||
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add %eax, %eax | ||
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# ALL: Iterations: 100 | ||
# ALL-NEXT: Instructions: 100 | ||
# ALL-NEXT: Total Cycles: 103 | ||
# ALL-NEXT: Dispatch Width: 2 | ||
# ALL-NEXT: IPC: 0.97 | ||
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# ALL: Instruction Info: | ||
# ALL-NEXT: [1]: #uOps | ||
# ALL-NEXT: [2]: Latency | ||
# ALL-NEXT: [3]: RThroughput | ||
# ALL-NEXT: [4]: MayLoad | ||
# ALL-NEXT: [5]: MayStore | ||
# ALL-NEXT: [6]: HasSideEffects | ||
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# ALL: [1] [2] [3] [4] [5] [6] Instructions: | ||
# ALL-NEXT: 1 1 0.50 addl %eax, %eax | ||
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# FULLREPORT: Dynamic Dispatch Stall Cycles: | ||
# FULLREPORT-NEXT: RAT - Register unavailable: 0 | ||
# FULLREPORT-NEXT: RCU - Retire tokens unavailable: 0 | ||
# FULLREPORT-NEXT: SCHEDQ - Scheduler full: 61 | ||
# FULLREPORT-NEXT: LQ - Load queue full: 0 | ||
# FULLREPORT-NEXT: SQ - Store queue full: 0 | ||
# FULLREPORT-NEXT: GROUP - Static restrictions on the dispatch group: 0 | ||
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# FULLREPORT: Dispatch Logic - number of cycles where we saw N instructions dispatched: | ||
# FULLREPORT-NEXT: [# dispatched], [# cycles] | ||
# FULLREPORT-NEXT: 0, 22 (21.4%) | ||
# FULLREPORT-NEXT: 2, 19 (18.4%) | ||
# FULLREPORT-NEXT: 1, 62 (60.2%) | ||
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# FULLREPORT: Schedulers - number of cycles where we saw N instructions issued: | ||
# FULLREPORT-NEXT: [# issued], [# cycles] | ||
# FULLREPORT-NEXT: 0, 3 (2.9%) | ||
# FULLREPORT-NEXT: 1, 100 (97.1%) | ||
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# FULLREPORT: Scheduler's queue usage: | ||
# FULLREPORT-NEXT: JALU01, 20/20 | ||
# FULLREPORT-NEXT: JFPU01, 0/18 | ||
# FULLREPORT-NEXT: JLSAGU, 0/12 | ||
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# FULLREPORT: Retire Control Unit - number of cycles where we saw N instructions retired: | ||
# FULLREPORT-NEXT: [# retired], [# cycles] | ||
# FULLREPORT-NEXT: 0, 3 (2.9%) | ||
# FULLREPORT-NEXT: 1, 100 (97.1%) | ||
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# FULLREPORT: Register File statistics: | ||
# FULLREPORT-NEXT: Total number of mappings created: 200 | ||
# FULLREPORT-NEXT: Max number of mappings used: 44 | ||
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# FULLREPORT: * Register File #1 -- FpuPRF: | ||
# FULLREPORT-NEXT: Number of physical registers: 72 | ||
# FULLREPORT-NEXT: Total number of mappings created: 0 | ||
# FULLREPORT-NEXT: Max number of mappings used: 0 | ||
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# FULLREPORT: * Register File #2 -- IntegerPRF: | ||
# FULLREPORT-NEXT: Number of physical registers: 64 | ||
# FULLREPORT-NEXT: Total number of mappings created: 200 | ||
# FULLREPORT-NEXT: Max number of mappings used: 44 | ||
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# FULLREPORT: Resources: | ||
# FULLREPORT-NEXT: [0] - JALU0 | ||
# FULLREPORT-NEXT: [1] - JALU1 | ||
# FULLREPORT-NEXT: [2] - JDiv | ||
# FULLREPORT-NEXT: [3] - JFPA | ||
# FULLREPORT-NEXT: [4] - JFPM | ||
# FULLREPORT-NEXT: [5] - JFPU0 | ||
# FULLREPORT-NEXT: [6] - JFPU1 | ||
# FULLREPORT-NEXT: [7] - JLAGU | ||
# FULLREPORT-NEXT: [8] - JMul | ||
# FULLREPORT-NEXT: [9] - JSAGU | ||
# FULLREPORT-NEXT: [10] - JSTC | ||
# FULLREPORT-NEXT: [11] - JVALU0 | ||
# FULLREPORT-NEXT: [12] - JVALU1 | ||
# FULLREPORT-NEXT: [13] - JVIMUL | ||
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# FULLREPORT: Resource pressure per iteration: | ||
# FULLREPORT-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] | ||
# FULLREPORT-NEXT: 0.50 0.50 - - - - - - - - - - - - | ||
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# FULLREPORT: Resource pressure by instruction: | ||
# FULLREPORT-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: | ||
# FULLREPORT-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax | ||
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats=false < %s | FileCheck %s -check-prefix=ALL | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats=false -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL | ||
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add %eax, %eax | ||
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# ALL: Iterations: 100 | ||
# ALL-NEXT: Instructions: 100 | ||
# ALL-NEXT: Total Cycles: 103 | ||
# ALL-NEXT: Dispatch Width: 2 | ||
# ALL-NEXT: IPC: 0.97 | ||
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# ALL: Instruction Info: | ||
# ALL-NEXT: [1]: #uOps | ||
# ALL-NEXT: [2]: Latency | ||
# ALL-NEXT: [3]: RThroughput | ||
# ALL-NEXT: [4]: MayLoad | ||
# ALL-NEXT: [5]: MayStore | ||
# ALL-NEXT: [6]: HasSideEffects | ||
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# ALL: [1] [2] [3] [4] [5] [6] Instructions: | ||
# ALL-NEXT: 1 1 0.50 addl %eax, %eax | ||
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# FULL: Dynamic Dispatch Stall Cycles: | ||
# FULL-NEXT: RAT - Register unavailable: 0 | ||
# FULL-NEXT: RCU - Retire tokens unavailable: 0 | ||
# FULL-NEXT: SCHEDQ - Scheduler full: 61 | ||
# FULL-NEXT: LQ - Load queue full: 0 | ||
# FULL-NEXT: SQ - Store queue full: 0 | ||
# FULL-NEXT: GROUP - Static restrictions on the dispatch group: 0 | ||
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# FULL: Dispatch Logic - number of cycles where we saw N instructions dispatched: | ||
# FULL-NEXT: [# dispatched], [# cycles] | ||
# FULL-NEXT: 0, 22 (21.4%) | ||
# FULL-NEXT: 2, 19 (18.4%) | ||
# FULL-NEXT: 1, 62 (60.2%) | ||
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# FULL: Schedulers - number of cycles where we saw N instructions issued: | ||
# FULL-NEXT: [# issued], [# cycles] | ||
# FULL-NEXT: 0, 3 (2.9%) | ||
# FULL-NEXT: 1, 100 (97.1%) | ||
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# FULL: Scheduler's queue usage: | ||
# FULL-NEXT: JALU01, 20/20 | ||
# FULL-NEXT: JFPU01, 0/18 | ||
# FULL-NEXT: JLSAGU, 0/12 | ||
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# FULL: Retire Control Unit - number of cycles where we saw N instructions retired: | ||
# FULL-NEXT: [# retired], [# cycles] | ||
# FULL-NEXT: 0, 3 (2.9%) | ||
# FULL-NEXT: 1, 100 (97.1%) | ||
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# FULL: Register File statistics: | ||
# FULL-NEXT: Total number of mappings created: 200 | ||
# FULL-NEXT: Max number of mappings used: 44 | ||
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# FULL: * Register File #1 -- FpuPRF: | ||
# FULL-NEXT: Number of physical registers: 72 | ||
# FULL-NEXT: Total number of mappings created: 0 | ||
# FULL-NEXT: Max number of mappings used: 0 | ||
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# FULL: * Register File #2 -- IntegerPRF: | ||
# FULL-NEXT: Number of physical registers: 64 | ||
# FULL-NEXT: Total number of mappings created: 200 | ||
# FULL-NEXT: Max number of mappings used: 44 | ||
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# FULL: Resources: | ||
# FULL-NEXT: [0] - JALU0 | ||
# FULL-NEXT: [1] - JALU1 | ||
# FULL-NEXT: [2] - JDiv | ||
# FULL-NEXT: [3] - JFPA | ||
# FULL-NEXT: [4] - JFPM | ||
# FULL-NEXT: [5] - JFPU0 | ||
# FULL-NEXT: [6] - JFPU1 | ||
# FULL-NEXT: [7] - JLAGU | ||
# FULL-NEXT: [8] - JMul | ||
# FULL-NEXT: [9] - JSAGU | ||
# FULL-NEXT: [10] - JSTC | ||
# FULL-NEXT: [11] - JVALU0 | ||
# FULL-NEXT: [12] - JVALU1 | ||
# FULL-NEXT: [13] - JVIMUL | ||
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# FULL: Resource pressure per iteration: | ||
# FULL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] | ||
# FULL-NEXT: 0.50 0.50 - - - - - - - - - - - - | ||
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# FULL: Resource pressure by instruction: | ||
# FULL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: | ||
# FULL-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax | ||
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@@ -0,0 +1,116 @@ | ||
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views < %s | FileCheck %s -check-prefix=ALL -check-prefix=DEFAULTREPORT -check-prefix=FULLREPORT | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=true < %s | FileCheck %s -check-prefix=ALL -check-prefix=DEFAULTREPORT -check-prefix=FULLREPORT | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOREPORT | ||
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=DEFAULTREPORT | ||
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add %eax, %eax | ||
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# ALL: Iterations: 100 | ||
# ALL-NEXT: Instructions: 100 | ||
# ALL-NEXT: Total Cycles: 103 | ||
# ALL-NEXT: Dispatch Width: 2 | ||
# ALL-NEXT: IPC: 0.97 | ||
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# DEFAULTREPORT: Instruction Info: | ||
# DEFAULTREPORT-NEXT: [1]: #uOps | ||
# DEFAULTREPORT-NEXT: [2]: Latency | ||
# DEFAULTREPORT-NEXT: [3]: RThroughput | ||
# DEFAULTREPORT-NEXT: [4]: MayLoad | ||
# DEFAULTREPORT-NEXT: [5]: MayStore | ||
# DEFAULTREPORT-NEXT: [6]: HasSideEffects | ||
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# DEFAULTREPORT: [1] [2] [3] [4] [5] [6] Instructions: | ||
# DEFAULTREPORT-NEXT: 1 1 0.50 addl %eax, %eax | ||
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# FULLREPORT: Dynamic Dispatch Stall Cycles: | ||
# FULLREPORT-NEXT: RAT - Register unavailable: 0 | ||
# FULLREPORT-NEXT: RCU - Retire tokens unavailable: 0 | ||
# FULLREPORT-NEXT: SCHEDQ - Scheduler full: 61 | ||
# FULLREPORT-NEXT: LQ - Load queue full: 0 | ||
# FULLREPORT-NEXT: SQ - Store queue full: 0 | ||
# FULLREPORT-NEXT: GROUP - Static restrictions on the dispatch group: 0 | ||
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# FULLREPORT: Dispatch Logic - number of cycles where we saw N instructions dispatched: | ||
# FULLREPORT-NEXT: [# dispatched], [# cycles] | ||
# FULLREPORT-NEXT: 0, 22 (21.4%) | ||
# FULLREPORT-NEXT: 2, 19 (18.4%) | ||
# FULLREPORT-NEXT: 1, 62 (60.2%) | ||
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# FULLREPORT: Schedulers - number of cycles where we saw N instructions issued: | ||
# FULLREPORT-NEXT: [# issued], [# cycles] | ||
# FULLREPORT-NEXT: 0, 3 (2.9%) | ||
# FULLREPORT-NEXT: 1, 100 (97.1%) | ||
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# FULLREPORT: Scheduler's queue usage: | ||
# FULLREPORT-NEXT: JALU01, 20/20 | ||
# FULLREPORT-NEXT: JFPU01, 0/18 | ||
# FULLREPORT-NEXT: JLSAGU, 0/12 | ||
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# FULLREPORT: Retire Control Unit - number of cycles where we saw N instructions retired: | ||
# FULLREPORT-NEXT: [# retired], [# cycles] | ||
# FULLREPORT-NEXT: 0, 3 (2.9%) | ||
# FULLREPORT-NEXT: 1, 100 (97.1%) | ||
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# FULLREPORT: Register File statistics: | ||
# FULLREPORT-NEXT: Total number of mappings created: 200 | ||
# FULLREPORT-NEXT: Max number of mappings used: 44 | ||
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# FULLREPORT: * Register File #1 -- FpuPRF: | ||
# FULLREPORT-NEXT: Number of physical registers: 72 | ||
# FULLREPORT-NEXT: Total number of mappings created: 0 | ||
# FULLREPORT-NEXT: Max number of mappings used: 0 | ||
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# FULLREPORT: * Register File #2 -- IntegerPRF: | ||
# FULLREPORT-NEXT: Number of physical registers: 64 | ||
# FULLREPORT-NEXT: Total number of mappings created: 200 | ||
# FULLREPORT-NEXT: Max number of mappings used: 44 | ||
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# FULLREPORT: Resources: | ||
# FULLREPORT-NEXT: [0] - JALU0 | ||
# FULLREPORT-NEXT: [1] - JALU1 | ||
# FULLREPORT-NEXT: [2] - JDiv | ||
# FULLREPORT-NEXT: [3] - JFPA | ||
# FULLREPORT-NEXT: [4] - JFPM | ||
# FULLREPORT-NEXT: [5] - JFPU0 | ||
# FULLREPORT-NEXT: [6] - JFPU1 | ||
# FULLREPORT-NEXT: [7] - JLAGU | ||
# FULLREPORT-NEXT: [8] - JMul | ||
# FULLREPORT-NEXT: [9] - JSAGU | ||
# FULLREPORT-NEXT: [10] - JSTC | ||
# FULLREPORT-NEXT: [11] - JVALU0 | ||
# FULLREPORT-NEXT: [12] - JVALU1 | ||
# FULLREPORT-NEXT: [13] - JVIMUL | ||
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# FULLREPORT: Resource pressure per iteration: | ||
# FULLREPORT-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] | ||
# FULLREPORT-NEXT: 0.50 0.50 - - - - - - - - - - - - | ||
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# FULLREPORT: Resource pressure by instruction: | ||
# FULLREPORT-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: | ||
# FULLREPORT-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax | ||
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# FULLREPORT: Timeline view: | ||
# FULLREPORT-NEXT: 012 | ||
# FULLREPORT-NEXT: Index 0123456789 | ||
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# FULLREPORT: [0,0] DeER . . . addl %eax, %eax | ||
# FULLREPORT-NEXT: [1,0] D=eER. . . addl %eax, %eax | ||
# FULLREPORT-NEXT: [2,0] .D=eER . . addl %eax, %eax | ||
# FULLREPORT-NEXT: [3,0] .D==eER . . addl %eax, %eax | ||
# FULLREPORT-NEXT: [4,0] . D==eER . . addl %eax, %eax | ||
# FULLREPORT-NEXT: [5,0] . D===eER . . addl %eax, %eax | ||
# FULLREPORT-NEXT: [6,0] . D===eER. . addl %eax, %eax | ||
# FULLREPORT-NEXT: [7,0] . D====eER . addl %eax, %eax | ||
# FULLREPORT-NEXT: [8,0] . D====eER. addl %eax, %eax | ||
# FULLREPORT-NEXT: [9,0] . D=====eER addl %eax, %eax | ||
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# FULLREPORT: Average Wait times (based on the timeline view): | ||
# FULLREPORT-NEXT: [0]: Executions | ||
# FULLREPORT-NEXT: [1]: Average time spent waiting in a scheduler's queue | ||
# FULLREPORT-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready | ||
# FULLREPORT-NEXT: [3]: Average time elapsed from WB until retire stage | ||
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# FULLREPORT: [0] [1] [2] [3] | ||
# FULLREPORT-NEXT: 0. 10 3.5 0.1 0.0 addl %eax, %eax | ||
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