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Initial commit of BCC S6 schematic files and gEDA project data.
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@emeb
emeb committed Oct 6, 2013
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10 changes: 10 additions & 0 deletions README.md
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===============

Hardware design files for the BCC S6

This project contains all the source required to build the Spartan 6 version of
the Blank Canvas Cape (BCC).. The BCC S6 is being designed entirely in gEDA/PCB
and targets a 4-layer PCB with 6mil/6mil design rules.

Find out more about the BCC at the main web page:

http://ebrombaugh.studionebula.com/embedded/bcc/index.html

Eric Brombaugh 12/31/2012
76 changes: 76 additions & 0 deletions bbb_pins.txt
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P8
PIN PROC PINCTRL ADDR NAME MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 MODE6 MODE7
* 3 R9 0x018 gpmc_ad6 gpmc_ad6 mmc1_dat6 gpio1[6]
* 4 T9 0x01c gpmc_ad7 gpmc_ad7 mmc1_dat7 gpio1[7]
* 5 R8 0x008 gpmc_ad2 gpmc_ad2 mmc1_dat2 gpio1[2]
* 6 T8 0x00c gpmc_ad3 gpmc_ad3 mmc1_dat3 gpio1[3]
* 7 R7 0x090 gpmc_advn_ale gpmc_advn_ale timer4 gpio2[2]
* 8 T7 0x094 gpmc_oen_ren gpmc_oen_ren timer7 gpio2[3]
* 9 T6 0x09c gpmc_be0n_cle gpmc_be0n_cle timer5 gpio2[5]
* 10 U6 0x098 gpmc_wen gpmc_wen timer6 gpio2[4]
* 11 R12 0x034 gpmc_ad13 gpmc_ad13 lcd_data18 mmc1_dat5 mmc2_dat1 eQEP2B_in gpio1[13]
* 12 T12 0x030 gpmc_ad12 gpmc_ad12 lcd_data19 mmc1_dat4 mmc2_dat0 eQEP2A_IN pru0_r31_14 gpio1[12]
* 13 T10 0x024 gpmc_ad9 gpmc_ad9 lcd_data22 mmc1_dat1 mmc2_dat5 ehrpwm2B pru0_r31_15 gpio0[23]
* 14 T11 0x028 gpmc_ad10 gpmc_ad10 lcd_data21 mmc1_dat2 mmc2_dat6 ehrpwm2_tripzone_in gpio0[26]
* 15 U13 0x03c gpmc_ad15 gpmc_ad15 lcd_data16 mmc1_dat7 mmc2_dat3 eQEP2_strobe pru0_r30_15 gpio1[15]
* 16 V13 0x038 gpmc_ad14 gpmc_ad14 lcd_data17 mmc1_dat6 mmc2_dat2 eQEP2_index pru0_r30_14 gpio1[14]
* 17 U12 0x02c gpmc_ad11 gpmc_ad11 lcd_data20 mmc1_dat3 mmc2_dat7 ehrpwm0_synco gpio0[27]
* 18 V12 0x08c gpmc_clk gpmc_clk lcd_memory_clk gpmc_wait1 mmc2_clk mcasp0_fsr gpio2[1]
* 19 U10 0x020 gpmc_ad8 gpmc_ad8 lcd_data23 mmc1_dat0 mmc2_dat4 ehrpwm2A gpio0[22]
* 20 V9 0x084 gpmc_csn2 gpmc_csn2 gpmc_be1n mmc1_cmd pru1_r30_13 pru1_r31_13 gpio1[31]
* 21 U9 0x080 gpmc_csn1 gpmc_csn1 gpmc_clk mmc1_clk pru1_r30_12 pru1_r31_12 gpio1[30]
* 22 V8 0x014 gpmc_ad5 gpmc_ad5 mmc1_dat5 gpio1[5]
* 23 U8 0x010 gpmc_ad4 gpmc_ad4 mmc1_dat4 gpio1[4]
* 24 V7 0x004 gpmc_ad1 gpmc_ad1 mmc1_dat1 gpio1[1]
* 25 U7 0x000 gpmc_ad0 gpmc_ad0 mmc1_dat0 gpio1[0]
* 26 V6 0x07c gpmc_csn0 gpmc_csn0 gpio1[29]
* 27 U5 0x0e0 lcd_vsync lcd_vsync gpmc_a8 pru1_r30_8 pru1_r31_8 gpio2[22]
* 28 V5 0x0e8 lcd_pclk lcd_pclk gpmc_a10 pru1_r30_10 pru1_r31_10 gpio2[24]
* 29 R5 0x0e4 lcd_hsync lcd_hsync gpmc_a9 pru1_r30_9 pru1_r31_9 gpio2[23]
* 30 R6 0x0ec lcd_ac_bias_en lcd_ac_bias_en gpmc_a11 pru1_r30_11 pru1_r31_11 gpio2[25]
bp 31 V4 0x0d8 lcd_data14 lcd_data14 gpmc_a18 eQEP1_index mcasp0_axr1 uart5_rxd uart5_ctsn gpio0[10]
bp 32 T5 0x0dc lcd_data15 lcd_data15 gpmc_a19 eQEP1_strobe mcasp0_ahclkx mcasp0_axr3 uart5_rtsn gpio0[11]
bp 33 V3 0x0d4 lcd_data13 lcd_data13 gpmc_a17 eQEP1B_in mcasp0_fsr mcasp0_axr3 uart4_rtsn gpio0[9]
bp 34 U4 0x0cc lcd_data11 lcd_data11 gpmc_a15 ehrpwm1B mcasp0_ahclkr mcasp0_axr2 uart3_rtsn gpio2[17]
bp 35 V2 0x0d0 lcd_data12 lcd_data12 gpmc_a16 eQEP1A_in mcasp0_aclkr mcasp0_axr2 uart4_ctsn gpio0[8]
bp 36 U3 0x0c8 lcd_data10 lcd_data10 gpmc_a14 ehrpwm1A mcasp0_axr0 uart3_ctsn gpio2[16]
bp 37 U1 0x0c0 lcd_data8 lcd_data8 gpmc_a12 ehrpwm1_tripzone_in mcasp0_aclkx uart5_txd uart2_ctsn gpio2[14]
bp 38 U2 0x0c4 lcd_data9 lcd_data9 gpmc_a13 ehrpwm0_synco mcasp0_fsx uart5_rxd uart2_rtsn gpio2[15]
*bp 39 T3 0x0b8 lcd_data6 lcd_data6 gpmc_a6 eQEP2_index pru1_r30_6 pru1_r31_6 gpio2[12]
*bp 40 T4 0x0bc lcd_data7 lcd_data7 gpmc_a7 eQEP2_strobe pr1_edio_data_out7 pru1_r30_7 pru1_r31_7 gpio2[13]
*bp 41 T1 0x0b0 lcd_data4 lcd_data4 gpmc_a4 eQEP2A_in pru1_r30_4 pru1_r31_4 gpio2[10]
*bp 42 T2 0x0b4 lcd_data5 lcd_data5 gpmc_a5 eQEP2B_in pru1_r30_5 pru1_r31_5 gpio2[11]
*bp 43 R3 0x0a8 lcd_data2 lcd_data2 gpmc_a2 ehrpwm2_tripzone_in pru1_r30_2 pru1_r31_2 gpio2[8]
*bp 44 R4 0x0ac lcd_data3 lcd_data3 gpmc_a3 ehrpwm0_synco pru1_r30_3 pru1_r31_3 gpio2[9]
*bp 45 R1 0x0a0 lcd_data0 lcd_data0 gpmc_a0 ehrpwm2A pru1_r30_0 pru1_r31_0 gpio2[6]
*bp 46 R2 0x0a4 lcd_data1 lcd_data1 gpmc_a1 ehrpwm2B pru1_r30_1 pru1_r31_1 gpio2[7]

P9
PIN PROC PINCTRL ADDR NAME MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 MODE6 MODE7
* 10 A10 RESET_OUT RESET_OUT
* 11 T17 0x070 gpmc_wait0 gpmc_wait0 mii2_crs gpmc_csn4 rmii2_crs_dv mmc1_sdcd uart4_rxd gpio0[30]
* 12 U18 0x078 gpmc_be1n gpmc_be1n mii2_col gpmc_csn6 mmc2_dat3 gpmc_dir mcasp0_aclkr gpio1[28]
13 U17 0x074 gpmc_wpn gpmc_wpn mii2_rxerr gpmc_csn5 rmii2_rxerr mmc2_sdcd uart4_txd gpio0[31]
14 U14 0x048 gpmc_a2 gpmc_a2 mii2_txd3 rgmii2_td3 mmc2_dat1 gpmc_a18 ehrpwm1A gpio1[18]
15 R13 0x040 gpmc_a0 gpmc_a0 gmii2_txen rmii2_tctl mii2_txen gpmc_a16 ehrpwm1_tripzone_input gpio1[16]
15 T13 0x088 gpmc_csn3 gpmc_csn3 gpmc_a3 rmii2_crs_dv mmc2_cmd pr1_mii0_crs pr1_mdio_data EMU4 gpio2[0]
16 T14 0x04c gpmc_a3 gpmc_a3 mii2_txd2 rgmii2_td2 mmc2_dat2 gpmc_a19 ehrpwm1B gpio1[19]
* 17 A16 0x15c spi0_cs0 spi0_cs0 mmc2_sdwp i2c1_scl ehrpwm0_synci gpio0[5]
* 18 B16 0x158 spi0_d1 spi0_d1 mmc1_sdwp i2c1_sda ehrpwm0_tripzone gpio0[4]
19 D17 0x17c uart1_rtsn uart1_rtsn timer5 dcan0_rx i2c2_scl spi1_cs1 gpio0[13]
20 D18 0x178 uart1_ctsn uart1_ctsn timer6 dcan0_tx i2c2_sda spi1_cs0 gpio0[12]
* 21 B17 0x154 spi0_d0 spi0_d0 uart2_txd i2c2_scl ehrpwm0B EMU3 gpio0[3]
* 22 A17 0x150 spi0_sclk spi0_sclk uart2_rxd i2c2_sda ehrpwm0A EMU2 gpio0[2]
23 V14 0x044 gpmc_a1 gpmc_a1 gmii2_rxdv rgmii2_rxdv mmc2_dat0 gpmc_a17 ehrpwm0_synco gpio1[17]
* 24 D15 0x184 uart1_txd uart1_txd mmc2_sdwp dcan1_rx i2c1_scl pru0_r31_16 gpio0[15]
* 25 A14 0x1ac mcasp0_ahclkx mcasp0_ahclkx eQEP0_strobe mcasp0_axr3 mcasp1_axr1 EMU4 pru0_r30_7 pru0_r31_7 gpio3[21]
* 26 D16 0x180 uart1_rxd uart1_rxd mmc1_sdwp dcan1_tx i2c1_sda pru1_r30_16 gpio0[14]
* 27 C13 0x1a4 mcasp0_fsr mcasp0_fsr eQEP0B_in mcasp0_axr3 mcasp1_fsx EMU2 pru0_r30_5 pru0_r31_5 gpio3[19]
* 28 C12 0x19c mcasp0_ahclkr mcasp0_ahclkr ehrpwm0_synci mcasp0_axr2 spi1_cs0 ecap2_in_pwm2_out pru0_r30_3 pru0_r31_3 gpio3[17]
* 29 B13 0x194 mcasp0_fsx mcasp0_fsx ehrpwm0B spi1_d0 mmc1_sdcd pru0_r30_1 pru0_r31_1 gpio3[15]
* 30 D12 0x198 mcasp0_axr0 mcasp0_axr0 ehrpwm0_tripzone spi1_d1 mmc2_sdcd pru0_r30_2 pru0_r31_2 gpio3[16]
* 31 A13 0x190 mcasp0_aclkx mcasp0_aclkx ehrpwm0A spi1_sclk mmc0_sdcd pru0_r30_0 pru0_r31_0 gpio3[14]
* 41 D14 0x1b4 xdma_event_intr1 xdma_event_intr1 tclkin clkout2 timer7 EMU3 gpio0[20]
* 41 D13 0x1A8 mcasp0_axr1 mcasp0_axr1 eQEPO_index mcasp1_axr0 EMU3 pru0_r30_6 pru0_r31_6 gpio3[20]
* 42 C18 0x164 ecap0_in_pwm0_out ecap0_in_pwm0_out uart3_txd spi1_cs1 pr1_ecap0_ecap_cap_in_apwm_o spi1_sclk mmc0_sdwp xdma_event_intr2 gpio0[7]
* 42 B12 0x1A0 mcasp0_aclkr mcasp0_aclkr eQEPO_in mcasp0_axr2 mcasp1_aclkx pru0_r30_4 pru0_r31_4 gpio3[18]
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