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A simple superscalar out-of-order RISC-V microprocessor
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
This repository contains the implementation of a single cycle based on RISC-V ISA and implemented on `LOGISIM`
Small Processing Unit 32: A compact RV32I CPU written in Verilog
A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)
A small and simple rv32i core written in Verilog
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
PulseRain Reindeer - RISCV RV32I[M] Soft CPU
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
A truck tracking project that can adapt to variable lighting conditions and narrow angles, providing a stable and reliable solution with YOLOv8.
SerialPortStream is an independent implementation of System.IO.Ports.SerialPort and SerialStream for better reliability and maintainability. Default branch is 2.x and now has support for Mono with …
Git ve GitHub'a yeni başlayanlar için ideal rehber! 🚀 Temel Git komutları, terimler ve takım çalışması konularına odaklanıyor. Python ve Streamlit kullanıldı, GitHub'da paylaşıldı. Hemen incele! 👀🌐
FPGA implementation of convolutional neural network with the dataset Fashion mnist
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
The schematic, layout, LVS & DRC checks of the layout and parasitic extraction of 3 input NAND and 2 input NOR
Simple cache design implementation in verilog
Verilog description of the Risc-V processor
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows