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Random test for slave and master connected
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -3,13 +3,9 @@ | |
| -- You can obtain one at http://mozilla.org/MPL/2.0/. | ||
| -- | ||
| -- Slawomir Siluk [email protected] 2018 | ||
| -- Wishbome Master Block Pipelined Bus Functional Model | ||
| -- Wishbome Master BFM for pipelined block transfers | ||
| -- TODO: | ||
| -- - stall input | ||
| -- - how to handle read req msg received while some writes | ||
| -- are still in progress? | ||
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| -- * Random strobe option | ||
| library ieee; | ||
| use ieee.std_logic_1164.all; | ||
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@@ -34,6 +30,7 @@ entity wishbone_master is | |
| cyc : out std_logic; | ||
| stb : out std_logic; | ||
| we : out std_logic; | ||
| stall : in std_logic; | ||
| ack : in std_logic | ||
| ); | ||
| end entity; | ||
|
|
@@ -88,7 +85,7 @@ begin | |
| cyc <= '1'; | ||
| stb <= '1'; | ||
| we <= '0'; | ||
| wait until rising_edge(clk); | ||
| wait until rising_edge(clk) and stall = '0'; | ||
| stb <= '0'; | ||
| push(acknowledge_queue, request_msg); | ||
| pending_acks := pending_acks +1; | ||
|
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@@ -102,7 +99,7 @@ begin | |
| cyc <= '1'; | ||
| stb <= '1'; | ||
| we <= '1'; | ||
| wait until rising_edge(clk); | ||
| wait until rising_edge(clk) and stall = '0'; | ||
| info(bus_handle.p_logger, "wr req"); | ||
| stb <= '0'; | ||
| push(acknowledge_queue, request_msg); | ||
|
|
@@ -121,6 +118,7 @@ begin | |
| received_acks := 0; | ||
| rd_cycle := false; | ||
| wr_cycle := false; | ||
| wait until rising_edge(clk); | ||
| end if; | ||
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|
||
| -- No cycles, juest sleep | ||
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||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -4,9 +4,6 @@ | |
| -- | ||
| -- Slawomir Siluk [email protected] 2018 | ||
| -- TODO: | ||
| -- - generic num_block_cycles | ||
| -- - generic adr and dat width | ||
| -- - generic random test | ||
| library ieee; | ||
| use ieee.std_logic_1164.all; | ||
| use ieee.numeric_std.all; | ||
|
|
@@ -22,12 +19,17 @@ library osvvm; | |
| use osvvm.RandomPkg.all; | ||
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| entity tb_wishbone_master is | ||
| generic (runner_cfg : string); | ||
| generic ( | ||
| runner_cfg : string; | ||
| dat_width : positive := 8; | ||
| adr_width : positive := 4; | ||
| num_cycles : positive := 1; | ||
| max_ack_dly : natural := 0; | ||
| rand_stall : boolean := false | ||
| ); | ||
| end entity; | ||
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| architecture a of tb_wishbone_master is | ||
| constant dat_width : positive := 8; | ||
| constant adr_width : positive := 4; | ||
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| signal clk : std_logic := '0'; | ||
| signal adr : std_logic_vector(adr_width-1 downto 0); | ||
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@@ -37,22 +39,22 @@ architecture a of tb_wishbone_master is | |
| signal cyc : std_logic := '0'; | ||
| signal stb : std_logic := '0'; | ||
| signal we : std_logic := '0'; | ||
| signal stall : std_logic := '0'; | ||
| signal ack : std_logic := '0'; | ||
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| constant master_logger : logger_t := get_logger("master"); | ||
| constant tb_logger : logger_t := get_logger("tb"); | ||
| constant bus_handle : bus_master_t := new_bus(data_length => dat_width, | ||
| address_length => adr_width, logger => master_logger); | ||
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| constant num_block_cycles : natural := 3; | ||
| begin | ||
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| main_stim : process | ||
| variable tmp : std_logic_vector(dat_i'range); | ||
| variable value : std_logic_vector(dat_i'range) := x"ab"; | ||
| variable bus_rd_ref1 : bus_reference_t; | ||
| variable bus_rd_ref2 : bus_reference_t; | ||
| type bus_reference_arr_t is array (0 to num_block_cycles-1) of bus_reference_t; | ||
| type bus_reference_arr_t is array (0 to num_cycles-1) of bus_reference_t; | ||
| variable rd_ref : bus_reference_arr_t; | ||
| begin | ||
| test_runner_setup(runner, runner_cfg); | ||
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@@ -75,43 +77,39 @@ begin | |
| -- check_equal(tmp, value, "read data"); | ||
| elsif run("wr block rd single") then | ||
| info(tb_logger, "Writing..."); | ||
| for i in 0 to num_block_cycles-1 loop | ||
| for i in 0 to num_cycles-1 loop | ||
| write_bus(net, bus_handle, i, | ||
| std_logic_vector(to_unsigned(i, dat_i'length))); | ||
| end loop; | ||
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| for i in 1 to num_block_cycles loop | ||
| for i in 1 to num_cycles loop | ||
| wait until ack = '1' and rising_edge(clk); | ||
| end loop; | ||
| wait until rising_edge(clk); | ||
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| info(tb_logger, "Reading..."); | ||
| for i in 0 to num_block_cycles-1 loop | ||
| for i in 0 to num_cycles-1 loop | ||
| read_bus(net, bus_handle, i, tmp); | ||
| check_equal(tmp, std_logic_vector(to_unsigned(i, dat_i'length)), "read data"); | ||
| end loop; | ||
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| elsif run("wr block rd block") then | ||
| info(tb_logger, "Writing..."); | ||
| for i in 0 to num_block_cycles-1 loop | ||
| for i in 0 to num_cycles-1 loop | ||
| write_bus(net, bus_handle, i, | ||
| std_logic_vector(to_unsigned(i, dat_i'length))); | ||
| end loop; | ||
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| -- Sleeping is needed to avoid wr and rd cycles coalescing | ||
| info(tb_logger, "Sleeping..."); | ||
| for i in 1 to num_block_cycles loop | ||
| wait until ack = '1' and rising_edge(clk); | ||
| end loop; | ||
| wait until rising_edge(clk); | ||
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| info(tb_logger, "Reading..."); | ||
| for i in 0 to num_block_cycles-1 loop | ||
| for i in 0 to num_cycles-1 loop | ||
| read_bus(net, bus_handle, i, rd_ref(i)); | ||
| end loop; | ||
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| info(tb_logger, "Get reads by references..."); | ||
| for i in 0 to num_block_cycles-1 loop | ||
| for i in 0 to num_cycles-1 loop | ||
| await_read_bus_reply(net, rd_ref(i), tmp); | ||
| check_equal(tmp, std_logic_vector(to_unsigned(i, dat_i'length)), "read data"); | ||
| end loop; | ||
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@@ -122,7 +120,7 @@ begin | |
| test_runner_cleanup(runner); | ||
| wait; | ||
| end process; | ||
| test_runner_watchdog(runner, 300 ns); | ||
| test_runner_watchdog(runner, 100 us); | ||
| set_format(display_handler, verbose, true); | ||
| show(tb_logger, display_handler, verbose); | ||
| show(default_logger, display_handler, verbose); | ||
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@@ -142,10 +140,15 @@ begin | |
| cyc => cyc, | ||
| stb => stb, | ||
| we => we, | ||
| stall => stall, | ||
| ack => ack | ||
| ); | ||
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| dut_slave : entity work.wishbone_slave | ||
| generic map ( | ||
| max_ack_dly => max_ack_dly, | ||
| rand_stall => rand_stall | ||
| ) | ||
| port map ( | ||
| clk => clk, | ||
| adr => adr, | ||
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@@ -155,6 +158,7 @@ begin | |
| cyc => cyc, | ||
| stb => stb, | ||
| we => we, | ||
| stall => stall, | ||
| ack => ack | ||
| ); | ||
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