Move stall probability to tb cfg

vunit/vhdl/verification_components/run.py

@@ -18,16 +18,16 @@
 
 
 def encode(tb_cfg):
-    return ", ".join(["%s:%s" % (key, str(tb_cfg[key])) for key in tb_cfg])
+    return ",".join(["%s:%s" % (key, str(tb_cfg[key])) for key in tb_cfg])
 
-def gen_wb_slave_tests(obj, dat_width, num_cycles, ack_prob, rand_stall):
-    for dat_width, num_cycles, ack_prob, rand_stall \
-    in product(dat_width, num_cycles, ack_prob, rand_stall):
+def gen_wb_slave_tests(obj, dat_width, num_cycles, ack_prob, stall_prob):
+    for dat_width, num_cycles, ack_prob, stall_prob \
+    in product(dat_width, num_cycles, ack_prob, stall_prob):
         tb_cfg = dict(
                 dat_width=dat_width,
                 adr_width=32,
                 ack_prob=ack_prob,
-                rand_stall=rand_stall,
+                stall_prob=stall_prob,
                 num_cycles=num_cycles
                 )
         config_name = encode(tb_cfg)
@@ -38,7 +38,7 @@ def gen_wb_slave_tests(obj, dat_width, num_cycles, ack_prob, rand_stall):
 tb_wishbone_slave = lib.test_bench("tb_wishbone_slave")
 
 for test in tb_wishbone_slave.get_tests():
-    gen_wb_slave_tests(test, [8, 32], [1, 64], [0.3, 1.0], [False, True])
+    gen_wb_slave_tests(test, [8, 32], [1, 64], [0.3, 1.0], [0.4, 0.0])
 
 
 def gen_wb_master_tests(obj, dat_width, num_cycles, ack_prob, rand_stall):

vunit/vhdl/verification_components/src/wishbone_pkg.vhd

@@ -15,7 +15,8 @@ context work.com_context;
 package wishbone_pkg is
 
   type wishbone_slave_t is record
-  	ack_high_probability : real range 0.0 to 1.0;
+    ack_high_probability : real range 0.0 to 1.0;
+    stall_high_probability : real range 0.0 to 1.0;
     -- Private
     p_actor : actor_t;
     p_ack_actor : actor_t;
@@ -27,6 +28,7 @@ package wishbone_pkg is
   impure function new_wishbone_slave(
     memory : memory_t;
     ack_high_probability : real := 1.0;
+    stall_high_probability : real := 0.0;
     logger : logger_t := wishbone_slave_logger)
     return wishbone_slave_t;
 
@@ -36,14 +38,16 @@ package body wishbone_pkg is
   impure function new_wishbone_slave(
     memory : memory_t;
     ack_high_probability : real := 1.0;
+    stall_high_probability : real := 0.0;
     logger : logger_t := wishbone_slave_logger)
     return wishbone_slave_t is
   begin
     return (p_actor => new_actor,
             p_ack_actor => new_actor,
             p_memory => to_vc_interface(memory, logger),
             p_logger => logger,
-            ack_high_probability => ack_high_probability
+            ack_high_probability => ack_high_probability,
+            stall_high_probability => stall_high_probability
         );
   end;
 

vunit/vhdl/verification_components/src/wishbone_slave.vhd

@@ -28,9 +28,7 @@ use osvvm.RandomPkg.all;
 
 entity wishbone_slave is
   generic (
-    wishbone_slave : wishbone_slave_t;
-    max_ack_dly : natural := 0;
-    rand_stall  : boolean := false
+    wishbone_slave : wishbone_slave_t
   );
   port (
     clk   : in std_logic;
@@ -97,9 +95,6 @@ begin
       data := (others => '0');
       addr := pop_integer(request_msg);
       data := read_word(wishbone_slave.p_memory, addr, sel'length);
-      for i in 1 to rnd.RandInt(0, max_ack_dly) loop
-        wait until rising_edge(clk);
-      end loop;
       while rnd.Uniform(0.0, 1.0) > wishbone_slave.ack_high_probability loop
         wait until rising_edge(clk);
       end loop;
@@ -113,17 +108,14 @@ begin
     end if;
   end process;
 
-  stall_stim_gen: if rand_stall generate
-    signal stall_l    : std_logic := '0';
-    begin
-    stall_stim: process
-      variable rnd : RandomPType;
-    begin
-      wait until rising_edge(clk) and cyc = '1';
-      stall_l <= rnd.RandSlv(1, 1)(0);
-    end process;
-    stall <= stall_l;
-  else generate
-    stall <= '0';
-  end generate;
+  stall_stim: process
+    variable rnd : RandomPType;
+  begin
+    if rnd.Uniform(0.0, 1.0) < wishbone_slave.stall_high_probability then
+      stall <= '1';
+    else
+      stall <= '0';
+    end if;
+    wait until rising_edge(clk) and cyc = '1';
+  end process;
 end architecture;

vunit/vhdl/verification_components/test/tb_wishbone_master.vhd

@@ -150,9 +150,7 @@ begin
 
   dut_slave : entity work.wishbone_slave
     generic map (
-      wishbone_slave => wishbone_slave,
-      max_ack_dly => max_ack_dly,
-      rand_stall => rand_stall
+      wishbone_slave => wishbone_slave
     )
     port map (
       clk   => clk,

vunit/vhdl/verification_components/test/tb_wishbone_slave.vhd

@@ -28,7 +28,7 @@ architecture a of tb_wishbone_slave is
     adr_width : positive;
     num_cycles : positive;
     ack_prob : real;
-    rand_stall : boolean;
+    stall_prob : real;
   end record tb_cfg_t;
 
   impure function decode(encoded_tb_cfg : string) return tb_cfg_t is
@@ -37,7 +37,7 @@ architecture a of tb_wishbone_slave is
             adr_width => positive'value(get(encoded_tb_cfg, "adr_width")),
             num_cycles => positive'value(get(encoded_tb_cfg, "num_cycles")),
             ack_prob => real'value(get(encoded_tb_cfg, "ack_prob")),
-            rand_stall => boolean'value(get(encoded_tb_cfg, "rand_stall")));
+            stall_prob => real'value(get(encoded_tb_cfg, "stall_prob")));
   end function decode;
 
   constant tb_cfg : tb_cfg_t := decode(encoded_tb_cfg);
@@ -62,7 +62,10 @@ architecture a of tb_wishbone_slave is
   constant memory : memory_t := new_memory;
   constant buf : buffer_t := allocate(memory, tb_cfg.num_cycles * sel'length);
   constant wishbone_slave : wishbone_slave_t :=
-      new_wishbone_slave(memory => memory, ack_high_probability => tb_cfg.ack_prob);
+      new_wishbone_slave(memory => memory,
+        ack_high_probability => tb_cfg.ack_prob,
+        stall_high_probability => tb_cfg.stall_prob
+      );
 begin
 
   main_stim : process
@@ -128,8 +131,7 @@ begin
 
   dut_slave : entity work.wishbone_slave
     generic map (
-      wishbone_slave => wishbone_slave,
-      rand_stall => tb_cfg.rand_stall
+      wishbone_slave => wishbone_slave
     )
     port map (
       clk   => clk,