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Issues: enjoy-digital/litex

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#614 opened Jul 31, 2020 by enjoy-digital
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Issues list

Error when trying to build base VexRiscV example on Alinx7203 Artix7 Board
#2184 opened Feb 16, 2025 by tarik-hamedovic
Converting Wishbone to riscv-steel custom bus new-feature question
#2178 opened Feb 7, 2025 by BMorgan1296
2
Support SD cards in DDR50 mode enhancement
#2177 opened Feb 6, 2025 by machdyne
1
litex_setup: Current --tag argument does not work answered-waiting-feedback bug?
#2175 opened Feb 4, 2025 by nickyu42
1
UART output garbled when building Litex SoC for CrossLinkNX with Radiant 2024.2 bug? regression
#2172 opened Feb 3, 2025 by polymerizedsage
2
Linking in libliteeth causes binary to fail to execute
#2157 opened Jan 13, 2025 by kscz
7
Please switch from setup-ghdl-ci to setup-ghdl
#2156 opened Jan 12, 2025 by Paebbels
Problem adding a new CPU answered-waiting-feedback install third-party-bug
#2155 opened Jan 7, 2025 by DaviLdM
2
Disabling interrupts in bios for serial boot, re-enabling when files are uploaded completely.
#2149 opened Dec 23, 2024 by Rajnesh28
1
Combination of --toolchain=openxc7 and --no-compile-gateware options
#2141 opened Dec 16, 2024 by Mecrisp
Memory initialization files answered-waiting-feedback
#2136 opened Dec 11, 2024 by merveyubogluu
3
Wishbone adapter to access flash through a movable window answered-waiting-feedback
#2134 opened Dec 3, 2024 by NateMeyer
3
SPI "Manual Operation useful for Bulk transfers" seems to do nothing
#2124 opened Nov 11, 2024 by YusufCelik
1
CVA6 + Nexys4 DDR - RAM access issues
#2121 opened Nov 8, 2024 by juanschroeder
2
litex_sim hangs when adding a call to a function in libliteeth
#2110 opened Oct 30, 2024 by jersey99
2
Implementing reset comming from the CPU jtag
#2109 opened Oct 28, 2024 by Dolu1990
Stuck at "liftoff" when I try romboot
#2108 opened Oct 27, 2024 by Stars-Collector
Cant have multiple Instances of Custom VHDL core
#2107 opened Oct 26, 2024 by Haron123
1
UartLite as a separate module.
#2096 opened Oct 15, 2024 by mohammadshahidzade
2
Generated Verilog project can't work
#2091 opened Oct 8, 2024 by snowprogrammer
2
RFC: Etherbone address detection
#2085 opened Sep 28, 2024 by m-byte
2
Simulate SoC and communicate through UART
#2084 opened Sep 28, 2024 by Leopard777
3
SPI flash not working with the ECP5 when using the Lattice Diamond toolchain
#2072 opened Sep 16, 2024 by dwalton65
Spi flash quad read not working with the ulx3s
#2064 opened Sep 11, 2024 by dwalton65
2
TIMER0 Interrupt
#2062 opened Sep 6, 2024 by gcourchinoux
3
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