Tags: ericchill/xed
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External Release v2022.10.11 Updated CPUs and instructions according to ISE (Intel Architecture Instruction Set Extensions and Future Features) rev-046, September 2022. Added: - Added new chips: Granite Rapids, Sierra Forest, Grand Ridge and Lakefield - Added new Instructions: AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPCCXADD, ICACHE_PREFETCH, MSRLIST, RAO-INT and WRMSRNS - Added getter API for VEX.pp prefix encoding value Fixed: - Fixed instructions-set list for SPR - Fixed first operand access definition for SSE compute instructions (intelxed#287) Modified: - Internal core modifications and updates
External Release v2022.08.11 General: - Drop KNC Support Added: - Support Clang14 static build (Resolves intelxed#283) Modified: - Examples: Improve encoding for non-vector 64bit GPR instructions - Examples: Support repeatable "-set" knob for setting multiple operands (xed.c and xed-ex1.c) Fixed: - Fixed decoder length check (ILD) for VEX instructions - Fixed STACKPUSH, STACKPOP registers definition - Fixed registers definition for the instructions: SWAPGS FXTRACT, F[,A]PTAN, and FSINCOS. - Fixed lock documentation (intelxed#280) - Improve EVEX Ubit handling and error detection
External Release v2022.04.17 Added: - Added AMX classifier API: xed_classify_amx() - Added CPUID bit definition for [F,]CMOV*, FCOMI* and MMX technology - Added AMX tests Modified: - Modified xed versioning to <year>.<month>.<day> - Improved re-encoding of vector instructions Fixed: - Fixed [LD,ST]TILECFG memory width definition - Fixed MOV[H,L,LH,HL]P[S,D] register's access definition - Fixed [,V]MASKMOVDQU register's element type - Fixed RING0 attribute for CLAC and STAC - Fixed JKZD/JKNZD VEX.L bit (intelxed#282) - Fixed KNC build and decoder - Fixed Clang13 build error for "-Werror=sign-compare" flag