A Visual environment which models Verilog (HDL) built on top of Google's Blockly API.

STUN / TURN standalone server

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Proxy: Next Generation Polymorphism in C++

Code-playground to visualise complex engineering flows.

Frame profiler

Single C file, Realtime CPU/GPU Profiler with Remote Web Viewer

microprofile is an embeddable profiler

A library of C++ coroutine abstractions for the coroutines TS

🌐 The Internet OS! Free, Open-Source, and Self-Hostable.

Secure & Modern All-in-One Mail Server (IMAP, JMAP, POP3, SMTP)

A simple superscalar out-of-order RISC-V microprocessor

A simple AXI4 DMA unit written in SpinalHDL.

A DMA Controller for RISCV CPUs

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

The missing CMake project initializer

Ansible playbooks for deploying a 3 node Kubernetes cluster

vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.

McuOnEclipse Processor Expert components and example projects

A secure embedded operating system for microcontrollers

RISC-V Instruction Set Manual

SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions

Artemis - The bugs hunter

DOULOS Easier UVM Code Generator

Scalene: a high-performance, high-precision CPU, GPU, and memory profiler for Python with AI-powered optimization proposals

A small framework to simplify the creation of custom instruction for the VexRiscv.